STR912FW44X6 STMicroelectronics, STR912FW44X6 Datasheet - Page 15

• Manufacturer Part Number: STR912FW44X6
• Description: MCU 512K FLASH 96K SRAM USB CAN
• Manufacturer: STMicroelectronics
• Series: STR9r

Specifications of STR912FW44X6

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• For Use With: 497-8267 - BOARD EVAL BASED ON STR9MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2497-5859 - EVAL BRD FULL USB DONGLE STR912MCBSTR9 - BOARD EVAL STM STR9 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5063-2; 497-5063-2; 497-5063-2ND; STR912FW44X6T

STR91xF
2.10.2 Reference clock (RCLK)
2.10.3 AHB clock (HCLK)
2.10.4 APB clock (PCLK)
2.10.5 Flash memory interface clock (FMICLK)
Figure 2.
The main clock (f
for the ARM core and all the peripherals. The RCLK provides the divided clock for the ARM
core, and feeds the dividers for the AHB, APB, External Memory Interface, and FMI units.
The RCLK can be divided by 1, 2 or 4 to generate the AHB clock. The AHB clock is the bus
clock for the AHB bus and all bus transfers are synchronized to this clock. The maximum HCLK
frequency is 96 MHz.
The RCLK can be divided by 1, 2, 4 or 8 to generate the APB clock. The APB clock is the bus
clock for the APB bus and all bus transfers are synchronized to this clock. Many of the
peripherals that are connected to the AHB bus also use the PCLK as the source for external
bus data transfers. The maximum PCLK frequency is 48 MHz.
The FMICLK clock is an internal clock derived from RCLK, defaulting to RCLK frequency at
power up. The clock can be optionally divided by 2. The FMICLK determines the bus bandwidth
between the ARM core and the Flash memory. Typically, codes in the Flash memory can be
fetched one word per FMICLK clock in burst mode. The maximum FMICLK frequency is
96MHz.
EXTCLK_T2T3
EXTCLK_T0T1
USB_CLK48M
MII_PHYCLK
X1_CPU
X1_RTC
X1_CPU
X2_RTC
JRTCLK
Clock control
4-25MHz
48MHz
25MHz
MSTR
4.096 kHz
16-bit prescaler
16-bit prescaler
) can be divided to operate at a slower frequency reference clock (RCLK)
Main
OSC
RTC
OSC
f
OSC
32.768 kHz
f
RTC
RTCSEL
PHYSEL
PLL
Timer 0 & 1
Timer 2 & 3
DIV8
f
PLL
Master CLK
f
MSTR
(1,2,4,8,16,1024)
1/2
1/2
RCLK
DIV
To USB
BRCLK
To UART
USBCLK
RCLK
1/2
1/2
Functional overview
AHB DIV
APB DIV)
(1,2,4)
(1,2,4,8)
CPUCLK
FMICLK
EMI_BCLK
PCLK
HCLK
15/73