STR911FM42X6 STMicroelectronics, STR911FM42X6 Datasheet - Page 25
![no-image](/images/manufacturer_photos/0/6/637/stmicroelectronics_sml.jpg)
STR911FM42X6
Manufacturer Part Number
STR911FM42X6
Description
MCU 256K FLASH 96K SRA, USB CAM
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet
1.STR910FM32X6.pdf
(73 pages)
Specifications of STR911FM42X6
Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, I²C, Microwire, SPI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
40
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-5060
497-5060-2
497-5060-2
STR911FM42X6T
497-5060-2
497-5060-2
STR911FM42X6T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
STR91xF
2.18.1 Packet buffer interface (PBI)
2.18.2 DMA
2.18.3 Suspend mode
2.19
●
●
●
●
●
●
●
The PBI manages a set of buffers inside the 2 Kbyte Packet Buffer, both for transmission and
reception. The PBI will choose the proper buffer according to requests coming from the USB
Serial Interface Engine (SIE) and locate it in the Packet SRAM according to addresses pointed
by endpoint registers. The PBI will also auto-increment the address after each exchanged byte
until the end of packet, keeping track of the number of exchanged bytes and preventing buffer
overrun. Special support is provided by the PBI for isochronous and bulk transfers,
implementing double-buffer usage which ensures there is always an available buffer for a USB
packet while the CPU uses a different buffer.
A programmable DMA channel may be assigned by CPU firmware to service the USB interface
for fast and direct transfers between the USB bus and SRAM with little CPU involvement. This
DMA channel includes the following features:
●
●
●
CPU firmware may place the USB interface in a low-power suspend mode when required, and
the USB interface will automatically wake up asynchronously upon detecting activity on the
USB pins.
CAN 2.0B interface
The STR91xF provides a CAN interface complying with CAN protocol version 2.0 parts A and
B. An external CAN transceiver device connected to pins CAN_RX and CAN_TX is required for
connection to the physical CAN bus.
The CAN interface manages up to 32 Message Objects and Identifier Masks using a Message
SRAM and a Message Handler. The Message Handler takes care of low-level CAN bus activity
such as acceptance filtering, transfer of messages between the CAN bus and the Message
Supports USB low and full-speed transfers (12 Mbps), certified to comply with the USB 2.0
specification
Supports isochronous, bulk, control, and interrupt endpoints
Configurable number of endpoints allowing a mixture of up to 20 single-buffered
monodirectional endpoints or up to 10 double-buffered bidirectional endpoints
Dedicated, dual-port 2 Kbyte USB Packet Buffer SRAM. One port of the SRAM is
connected by a Packet Buffer Interface (PBI) on the USB side, and the CPU connects to
the other SRAM port.
CRC generation and checking
NRZI encoding-decoding and bit stuffing
USB suspend resume operations
Direct USB Packet Buffer SRAM to system SRAM transfers of receive packets, by
descriptor chain for bulk or isochronous endpoints.
Direct system SRAM to USB Packet Buffer SRAM transfers of transmit packets, by
descriptor chain for bulk or isochronous endpoints.
Linked-list descriptor chain support for multiple USB packets
Functional overview
25/73