STR911FM42X6 STMicroelectronics, STR911FM42X6 Datasheet - Page 11
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STR911FM42X6
Manufacturer Part Number
STR911FM42X6
Description
MCU 256K FLASH 96K SRA, USB CAM
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet
1.STR910FM32X6.pdf
(73 pages)
Specifications of STR911FM42X6
Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, I²C, Microwire, SPI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
40
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-5060
497-5060-2
497-5060-2
STR911FM42X6T
497-5060-2
497-5060-2
STR911FM42X6T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
STR91xF
2.7.1
2.7.2
2.8
2.9
Flash memories are programmed half-word (16 bits) at a time, but are erased by sector or by
full array.
Primary Flash memory
Using the STR91xF device configuration software tool and 3rd party Integrated Developer
Environments, it is possible to specify that the primary Flash memory is the default memory
from which the CPU boots at reset, or otherwise specify that the secondary Flash memory is
the default boot memory. This choice of boot memory is non-volatile and stored in a location
that can be programmed and changed only by JTAG In-System Programming. See
Memory
The primary Flash memory has equal length 64K byte sectors. Devices with 256 Kbytes of
primary Flash have four sectors and 512K devices have eight sectors.
Secondary Flash memory
The smaller of the two Flash memories can be used to implement a bootloader, capable of
storing code to perform robust In-Application Programming (IAP) of the primary Flash memory.
The CPU executes code from the secondary Flash, while updating code in the primary Flash
memory. New code for the primary Flash memory can be downloaded over any of the
interfaces on the STR91xF (USB, Ethernet, CAN, UART, etc.)
Additionally, the Secondary Flash memory may also be used to store small data sets by
emulating EEPROM though firmware, eliminating the need for external EEPROM memories.
This raises the data security level because passcodes and other sensitive information can be
securely locked inside the STR91xF device.
The secondary Flash memory is 32 Kbytes and has four equal length sectors of 8 Kbytes each.
Both the primary Flash memory and the secondary Flash memory can be programmed with
code and/or data using the JTAG In-System Programming (ISP) channel, totally independent of
the CPU. This is excellent for iterative code development and for manufacturing.
One-time-programmable (OTP) memory
There are 32 bytes of OTP memory ideally suited for serial numbers, security keys, factory
calibration constants, or other permanent data constants. These OTP data bytes can be
programmed only one time through either the JTAG interface or by the CPU, and these bytes
can never be altered afterwards. As an option, a “lock bit” can be set by the JTAG interface or
the CPU which will block any further writing to the this OTP area. The “lock bit” itself is also
OTP. If the OTP array is unlocked, it is always possible to go back and write to an OTP byte
location that has not been previously written, but it is never possible to change an OTP byte
location if any one bit of that particular byte has been written before. The last two OTP bytes are
reserved for the STR91xF product ID and revision level. Byte 30 contains the device revision
level. For STR91xF devices, the revision is 0x13.
Vectored interrupt controller (VIC)
Interrupt management in the STR91xF is implemented from daisy-chaining two standard ARM
VIC units. This combined VIC has 32 prioritized interrupt request channels and generates two
mapping, for more detail.
Functional overview
Section 5:
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