STR911FM42X6 STMicroelectronics, STR911FM42X6 Datasheet - Page 13
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STR911FM42X6
Manufacturer Part Number
STR911FM42X6
Description
MCU 256K FLASH 96K SRA, USB CAM
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet
1.STR910FM32X6.pdf
(73 pages)
Specifications of STR911FM42X6
Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, I²C, Microwire, SPI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
40
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-5060
497-5060-2
497-5060-2
STR911FM42X6T
497-5060-2
497-5060-2
STR911FM42X6T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
STR91xF
See
Interrupt source assignments are made by CPU firmware during initialization, thus establishing
interrupt priorities.
Table 2.
VIC IRQ Channel
31 (low priority)
0 (high priority)
Table 2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
Recommended IRQ Channel assignments (set by CPU firmware)
for recommended interrupt source assignments to physical IRQ interrupt channels.
Wake-up Group 0
Wake-up Group 1 Logic OR of 8 interrupts from pins P5.0 to P5.7
Wake-up Group 2 Logic OR of 8 interrupts from pins P6.0 to P6.7
Wake-up Group 3 Logic OR of 8 interrupts from pins P7.0 to P7.7
CPU Firmware
Ethernet MAC
Wake-Up (all)
BROWNOUT
Logic Block
TIM Timer 0
TIM Timer 1
TIM Timer 2
TIM Timer 3
WatchDog
CPU Core
CPU Core
PFQ-BC
UART0
UART1
UART2
SSP0
SSP1
CCU
DMA
USB
USB
CAN
ADC
I2C0
I2C1
RTC
USB
IMC
Timeout in WDT mode, Terminal Count in Counter Mode
Firmware generated interrupt
Debug Receive Command
Debug Transmit Command
Logic OR of ICI0_0, ICI0_1, OCI0_0, OCI0_1, Timer overflow
Logic OR of ICI1_0, ICI1_1, OCI1_0, OCI1_1, Timer overflow
Logic OR of ICI2_0, ICI2_1, OCI2_0, OCI2_1, Timer overflow
Logic OR of ICI3_0, ICI3_1, OCI3_0, OCI3_1, Timer overflow
Logic OR of high priority USB interrupts
Logic OR of low priority USB interrupts
Logic OR of all interrupts from Clock Control Unit
Logic OR of Ethernet MAC interrupts via its own dedicated
DMA channel.
Logic OR of interrupts from each of the 8 individual DMA
channels
Logic OR of all CAN interface interrupt sources
Logic OR of 8 Induction Motor Control Unit interrupts
End of AtoD conversion interrupt
Logic OR of 5 interrupts from UART channel 0
Logic OR of 5 interrupts from UART channel 1
Logic OR of 5 interrupts from UART channel 2
Logic OR of transmit, receive, and error interrupts of I2C
channel 0
Logic OR of transmit, receive, and error interrupts of I2C
channel 1
Logic OR of all interrupts from SSP channel 0
Logic OR of all interrupts from SSP channel 1
LVD warning interrupt
Logic OR of Alarm, Tamper, or Periodic Timer interrupts
Logic OR of all 32 inputs of Wake-Up unit (30 pins, RTC, and
USB Resume)
Logic OR of 8 interrupt sources: RTC, USB Resume, pins
P3.2 to P3.7
USB Bus Resume Wake-up (also input to wake-up unit)
Special use of interrupts from Prefetch Queue and Branch
Cache
Interrupt Source
Functional overview
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