ST92F150JDV1QC STMicroelectronics, ST92F150JDV1QC Datasheet - Page 354

• Manufacturer Part Number: ST92F150JDV1QC
• Description: IC MCU 128K FLASH 100-PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150JDV1QC

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2137

CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
CAN FILTER CONFIGURATION REG.2 (CFCR2)
All bits of this register are set and cleared by soft-
ware.
Read / Write
Reset Value: 0000 0000 (00h)
Note: To modify FFAx and FSCx bits bxCAN must
be in INIT mode.
Bit 7 = FFA5 Filter FIFO Assignment for Filter 5
The message passing through this filter will be
stored in the specified FIFO.
0: Filter assigned to FIFO 0
1: Filter assigned to FIFO 1
Bit 6:5 = FSC5[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
5.
Bit 4 = FACT5 Filter Active
The software sets this bit to activate Filter 5. To
modify the filter 5 registers (CF5R[7:0]), the
FACT5 bit must be cleared.
0: Filter 5 is not active
1: Filter 5 is active
Bit 3 = FFA4 Filter FIFO Assignment for Filter 4
The message passing through this filter will be
stored in the specified FIFO.
0: Filter assigned to FIFO 0
1: Filter assigned to FIFO 1
Bit 2:1 = FSC4[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
4.
Bit 0 = FACT4 Filter Active
The software sets this bit to activate filter 4. To
modify the Filter 4 registers (CF4R[7:0]), the
FACT4 bit must be cleared).
0: Filter 4 is not active
1: Filter 4 is active
354/429
9
FFA5 FSC51 FSC50 FACT5 FFA4 FSC41 FSC40 FACT4
7
0
CAN FILTER CONFIGURATION REG.3 (CFCR3)
All bits of this register are set and cleared by soft-
ware.
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 = FFA7 Filter FIFO Assignment for Filter 7
The message passing through this filter will be
stored in the specified FIFO.
0: Filter assigned to FIFO 0
1: Filter assigned to FIFO 1
Bit 6:5 = FSC7[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
7.
Bit 4 = FACT7 Filter Active
The software sets this bit to activate Filter 7. To
modify the Filter 7 registers (CF7R[7:0]), the
FACT7 bit must be cleared.
0: Filter 7 is not active.
1: Filter 7 is active.
Bit 3 = FFA6 Filter FIFO Assignment for Filter 6
This bit allows the software to define whether the
message passing through this filter will be as-
signed to the receive FIFO0 or FIFO1.
0: Filter assigned to FIFO 0
1: Filter assigned to FIFO 1
Bit 2:1 = FSC6[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
6.
Bit 0 = FACT6 Filter Active
The software sets this bit to activate Filter 6. To
modify the Filter 6 registers (CF6R[7:0]), the
FACT6 bit must be cleared.
0: Filter 6 is not active
1: Filter 6 is active
FFA7 FSC71 FSC70 FACT7 FFA6 FSC61 FSC60 FACT6
7
0