SX18AC/SO Parallax Inc, SX18AC/SO Datasheet - Page 9

• Manufacturer Part Number: SX18AC/SO
• Description: IC MCU 2K FLASH 50MHZ SO-18
• Manufacturer: Parallax Inc
• Series: SXr

Specifications of SX18AC/SO

• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 50MHz
• Number Of I /o: 12
• Program Memory Size: 3KB (2K x 12)
• Program Memory Type: FLASH
• Ram Size: 137 x 8
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -

LVL_A, LVL_B, and LVL_C: Input Level Registers
(MODE=0Dh)
Each register bit determines the voltage levels sensed on
the input port, either TTL or CMOS, when the Schmitt
trigger option is disabled. Program each bit according to
the type of device that is driving the port input pin. Set the
bit to 1 for TTL or clear the bit to 0 for CMOS.
ST_B and ST_C: Schmitt Trigger Enable Registers
(MODE=0Ch)
Each register bit determines whether the port input pin
operates with a Schmitt trigger. Set the bit to 1 to disable
Schmitt trigger operation and sense either TTL or CMOS
voltage levels; or clear the bit to 0 to enable Schmitt trig-
ger operation.
WKEN_B: Wakeup Enable Register (MODE=0Bh)
Each register bit enables or disables the Multi-Input
Wakeup/Interrupt (MIWU) function for the corresponding
Port B input pin. Clear the bit to 0 to enable MIWU opera-
tion or set the bit to 1 to disable MIWU operation. For
more information on using the Multi-Input Wakeup/Inter-
rupt function, see Section 7.1.
WKED_B: Wakeup Edge Register (MODE=0Ah)
Each register bit selects the edge sensitivity of the Port B
input pin for MIWU operation. Set the bit to 1 to sense ris-
ing (low-to-high) edges. Clear the bit to 0 to sense falling
(high-to-low) edges.
© 1998 Scenix Semiconductor, Inc. All rights reserved.
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WKPND_B: Wakeup Pending Flag Register
(MODE=09h)
When you access the WKPND_B register using MOV
!RB,W, the CPU does an exchange between the contents
of W and WKPND_B. This feature lets you read the
WKPND_B register contents. Each bit indicates the sta-
tus of the corresponding MIWU pin. A bit set to 1 indi-
cates
corresponding MIWU pin, triggering a wakeup or inter-
rupt. A bit set to 0 indicates that no valid edge has
occurred on the MIWU pin.
CMP_B: Comparator Register (MODE=08h)
When you access
!RB,W, the CPU does an exchange between the contents
of W and CMP_B. This feature lets you read the CMP_B
register contents. Clear bit 7 to enable operation of the
comparator. Clear bit 6 to place the comparator result on
the RB0 pin. Bit 0 is a result flag that is set to 1 when the
voltage on RB2 is greater than RB1, or cleared to 0 oth-
erwise. (For more information using the comparator, see
Section 11.0.)
3.2.3 Port Configuration Upon Power-Up
Upon power-up, all the port control registers are initial-
ized to FFh. Thus, each pin is configured to operate as a
high-impedance input that senses TTL voltage levels,
with no internal pullup resistor connected. The MODE
register is initialized to 0Fh, which allows immediate
access to the data direction registers using the “MOV
!rx,W” instruction.
that
a
valid
the CMP_B register using MOV
edge
SX18AC / SX20AC / SX28AC
has
occurred
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on
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