SX18AC/SO Parallax Inc, SX18AC/SO Datasheet - Page 18

• Manufacturer Part Number: SX18AC/SO
• Description: IC MCU 2K FLASH 50MHZ SO-18
• Manufacturer: Parallax Inc
• Series: SXr

Specifications of SX18AC/SO

• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 50MHz
• Number Of I /o: 12
• Program Memory Size: 3KB (2K x 12)
• Program Memory Type: FLASH
• Ram Size: 137 x 8
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -

SX18AC / SX20AC / SX28AC
8.0 INTERRUPT SUPPORT
The device supports both internal and external maskable
interrupts. The internal interrupt is generated as a result
of the RTCC rolling over from 0FFh to 00h. This interrupt
source has an associated enable bit located in the
OPTION register. There is no pending flag associated
with this interrupt.
Port B provides the source for eight external software
selectable, edge sensitive interrupts, when the device is
not in the SLEEP mode. These interrupt sources share
logic with the Multi-Input Wakeup circuitry. The WKEN_B
register allows interrupt from Port B to be individually
enabled or disabled. Clearing a bit in the WKEN_B regis-
ter enables the interrupt on the corresponding Port B pin.
All interrupts are global in nature; that is, no interrupt has
priority over another. Interrupts are handled sequentially.
Figure 8-2 shows the interrupt processing sequence.
Once an interrupt is acknowledged, all subsequent global
interrupts are disabled until return from servicing the cur-
rent interrupt. The PC is pushed onto the single level
interrupt stack, and the contents of the FSR, STATUS,
and W registers are saved in their corresponding shadow
registers. The interrupt logic has its own single-level
stack and is not part of the CALL subroutine stack. The
vector for the interrupt service routines is address 0.
Once in the interrupt service routine, the user program
must poll all external interrupt pending bits to determine
the source of the interrupt. The interrupt service routine
should clear the corresponding interrupt pending flag.
The user program may also need to read the contents of
© 1998 Scenix Semiconductor, Inc. All rights reserved.
WKPND_B
WKED_B
STATUS
PD
WKPND_B
WKED_B
1 = Ext Interrupt through Port B
0 = Sleep Mode, no Ext Interrupt
0
From MODE
(Mode = 09)
Figure 8-1. Interrupt Structure
OPTION
RTE_IE
- 18 -
RTCC
Overflow
The WKED_B selects the transition edge to be either
positive or negative. The WKEN_B and WKED_B regis-
ters are cleared upon reset. Setting a bit in the WKED_B
register selects the falling edge while resetting the bit
selects the rising edge on the corresponding Port B pin.
The WKPND_B register serves as the external interrupt
pending register.
The WKPND_B register comes up a with random value
upon reset. The user program must clear the WKPND_B
register prior to enabling the interrupt. The proper
sequence is described in Section 7.2 .
Figure 8-1 shows the structure of the interrupt logic.
RTCC to determine any recent RTCC rollover. This is
needed since there is no interrupt pending flag associ-
ated with the RTCC rollover.
Upon return from the interrupt service routine, the con-
tents of PC, FSR, STATUS, and W registers are restored
from their corresponding shadow registers. The interrupt
service routine should end with instructions such as RETI
and RETIW. RETI pops the interrupt stack and the spe-
cial shadow registers used for storing W, STATUS, and
FSR (preserved during interrupt handling). RETIW
behaves like RETI but also writes the literal to RTCC.
The interrupt return instruction enables the global inter-
rupts.
WKEN_B
Port B PIN
000
PC
Interrupt
Interrupt Stack
PC
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