SX18AC/SO Parallax Inc, SX18AC/SO Datasheet - Page 11
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SX18AC/SO
Manufacturer Part Number
SX18AC/SO
Description
IC MCU 2K FLASH 50MHZ SO-18
Manufacturer
Parallax Inc
Series
SXr
Datasheet
1.SX18ACSO.pdf
(43 pages)
Specifications of SX18AC/SO
Core Processor
RISC
Core Size
8-Bit
Speed
50MHz
Number Of I /o
12
Program Memory Size
3KB (2K x 12)
Program Memory Type
FLASH
Ram Size
137 x 8
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
18-SOIC
Voltage - Supply (vcc/vdd)
-
Eeprom Size
-
Data Converters
-
Peripherals
-
Connectivity
-
4.3 OPTION Register
When the OPTIONX bit in the FUSE word is cleared, bits
7 and 6 of the OPTION register are implemented.
When the OPTIONX bit is set, bits 7 and 6 of the
OPTION register read as ‘1’s.
© 1998 Scenix Semiconductor, Inc. All rights reserved.
RTW
RTE_IE
RTS
RTE_ES
PSA
PS2-PS0
RTW RTE
Bit 7
_IE
RTCC/W register selection:
0 = Register 01h addresses W
1 = Register 01h addresses RTCC
RTCC edge interrupt enable:
0 = RTCC roll-over interrupt is enabled
1 = RTCC roll-over interrupt is disabled
RTCC increment select:
0 = RTCC increments on internal instruction
cycle
1 = RTCC increments upon transition on
RTCC pin
RTCC edge select:
0 = RTCC increments on low-to-high transi-
tions
1 = RTCC increments on high-to-low transi-
tions
Prescaler Assignment:
0 = Prescaler is assigned to RTCC, with di-
vide rate determined by PS0-PS2 bits
1 = Prescaler is assigned to WDT, and divide
rate on RTCC is 1:1
Prescaler divider (see Table 4-2)
RTS
RTE
_ES
PSA
PS2
PS1
Bit 0
PS0
- 11 -
Upon reset, all bits in the OPTION register are set to 1.
PS2, PS1, PS0
000
001
010
011
100
101
110
111
Table 4-2. Prescaler Divider Ratios
Divide Rate
RTCC
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
SX18AC / SX20AC / SX28AC
Watchdog Timer
Divide Rate
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
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