SX18AC/SO Parallax Inc, SX18AC/SO Datasheet - Page 28

• Manufacturer Part Number: SX18AC/SO
• Description: IC MCU 2K FLASH 50MHZ SO-18
• Manufacturer: Parallax Inc
• Series: SXr

Specifications of SX18AC/SO

• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 50MHz
• Number Of I /o: 12
• Program Memory Size: 3KB (2K x 12)
• Program Memory Type: FLASH
• Ram Size: 137 x 8
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -

SX18AC / SX20AC / SX28AC
15.4 RAM Addressing
Direct Addressing
The FSR register must initialized with an appropriate
value in order to address the desired RAM register. The
following table and code example show how to directly
access the banked registers.
Indirect Addressing
To access any register via indirect addressing, simply
move the eight-bit address of the desired register into the
FSR and use INDF as the operand. The example below
shows how to clear all RAM locations from 10h to 1Fh in
all eight banks:
15.5 The Bank Instruction
Often it is desirable to set the bank select bits of the FSR
register in one instruction cycle. The Bank instruction
provides this capability. This instruction sets the upper
bits of the FSR to point to a specific RAM bank without
affecting the other FSR bits.
Example:
15.6 Bit Manipulation
The instruction set contains instructions to set, reset, and
test individual bits in data memory. The device is capable
of bit addressing anywhere in data memory.
© 1998 Scenix Semiconductor, Inc. All rights reserved.
:loop
mov
clr
mov
clr
bank $F0
inc
clr
setb
clr
incsz FSR
jmp
FSR,#$070
$010
FSR,#$D0
$010
$1F
Bank
FSR
SFR.4
INDF
:loop
0
1
2
3
4
5
6
7
;Select Bank 7 in FSR
;increment file register
;1Fh in Bank 7
;clear FSR to 00h (at address
;04h)
;set bit 4: address 10h-1Fh,
;30-3Fh, etc
;clear register pointed to by
;FSR
;increment FSR and test, skip
;jmp if 00h
;jump back and clear next
;register
;Select RAM Bank 3
;Clear register 10h on
;Bank 3
;Select RAM Bank 6
;Clear register 10h on
;Bank 6
FSR Value
0D0h
010h
030h
050h
070h
090h
0B0h
0F0h
- 28 -
15.7 Input/Output Operation
The device contains three registers associated with each
I/O port. The first register (Data Direction Register), con-
figures each port pin as a Hi-Z input or output. The sec-
ond register (TTL/CMOS Register), selects the desired
input level for the input. The third register (Pull-Up Regis-
ter), enables a weak pull-up resistor on the pin configured
as a input. In addition to using the associated port regis-
ters, appropriate values must be written into the MODE
register to configure the I/O ports.
15.7.1 Read-Modify-Write Considerations
Caution must be exercised when performing successive
SETB or CLRB operations on I/O port pin. Input data
used for an instruction must be valid during the time the
instruction is executed, and the output result from an
instruction is valid only after that instruction completes its
operation. Unexpected results from successive read-
modify-write operations on I/O pins can occur when the
device is running at extremely high speeds. Although the
device has an internal write-back section to prevent such
conditions, it is still recommended that the user program
include a NOP instruction as a buffer between succes-
sive read-modify-write instructions performed on I/O pins
of the same port.
Also note that reading an I/O port is actually reading the
pins, not the output data latches. That is, if the pin output
driver is enabled and driven high while the pin is held low
externally, the port pin will read low.
15.8 Increment/Decrement
The bank of 31 registers serves as a set of accumulators.
The instruction set contains instructions to increment and
decrement the register file. The device also includes both
INCSZ fr (increment file register and skip if zero) and
DECSZ fr (decrement file register and skip if zero)
instructions.
15.9 Loop Counting and Data Pointing
The device has specific instructions to facilitate loop
counting. The DECSZ fr (decrement file register and skip
if zero) tests any one of the file registers and skips the
next instruction (which can be a branch back to loop) if
the result is zero.
15.10 Branch and Loop Call Instructions
The device contains an 8-level hardware stack where the
return address is stored with a subroutine call. Multiple
stack levels allow subroutine nesting. The instruction set
supports absolute address branching.
15.10.1 Jump Operation
When a JMP instruction is executed, the lower nine bits
of the program counter is loaded with the address of the
specified label. The upper two bits of the program
counter are loaded with the page select bits, PA1:PA0,
contained in the STATUS register. Therefore, care must
be exercised to ensure the page select bits are pointing
to the correct page before the jump occurs.
Testing
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