SX18AC/SO Parallax Inc, SX18AC/SO Datasheet - Page 24

• Manufacturer Part Number: SX18AC/SO
• Description: IC MCU 2K FLASH 50MHZ SO-18
• Manufacturer: Parallax Inc
• Series: SXr

Specifications of SX18AC/SO

• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 50MHz
• Number Of I /o: 12
• Program Memory Size: 3KB (2K x 12)
• Program Memory Type: FLASH
• Ram Size: 137 x 8
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -

SX18AC / SX20AC / SX28AC
12.0 RESET
Power-On-Reset, Brown-Out reset, watchdog reset, or
external reset initializes the device. Each one of these
reset conditions causes the program counter to branch to
the top of the program memory. For example, on the
device with 2K of program memory, the program counter
is initialized to 07FF.
The device incorporates an on-chip Power-On Reset
(POR) circuit that generates an internal reset as V
during power-up. Figure 12-1 is a block diagram of the
circuit. The circuit contains an 8-bit Delay Reset Timer
(DRT) and a reset latch. The DRT controls the reset time-
out delay. The reset latch controls the internal reset sig-
nal. Upon power-up, the reset latch is set (device held in
reset), and the DRT starts counting once it detects a valid
logic high signal at the MCLR pin. Once DRT reaches the
end of the timeout period (typically 72 msec), the reset
latch is cleared, releasing the device from reset state.
Note:Ripple counter is 10 bits for Power on Reset (POR)
only.
Figure 12-2 shows a power-up sequence where MCLR is
not tied to the V
and stabilize before MCLR pin is brought high. The
device will actually come out of reset T
MCLR goes high.
The brown-out circuitry resets the chip when device
power (V
not to zero, and then recovers to the normal value.
Figure 12-3
sequence where the MCLR and V
together. The V
out period expires. In this case, the device will receive a
proper reset. However, Figure 12-4 depicts a situation
where V
time-out prior to V
level (V
reset and start operating with the supply voltage not at a
valid level. In this situation, it is recommended that you
use the external RC circuit shown in Figure 12-5. The RC
© 1998 Scenix Semiconductor, Inc. All rights reserved.
Figure 12-1. Block Diagram of On-Chip Reset Circuit
V
dd
MCLR/Vpp pin
rc_clk
dd
BROWN-OUT
dd
dd
min). This means the device will come out of
rises too slowly. In this scenario, the DRT will
) dips below its minimum allowed value, but
POR
shows
dd
dd
(DRT Start-Up
10-Bit Asynch
signal is stable before the DRT time-
dd
pin and V
Counter
Ripple
Timer)
reaching a valid operating voltage
POR
the
wdt_time_out
on-chip
dd
drt_time
signal is allowed to rise
_out
MIWU
Power-On
dd
S
R
drt
pins are tied
enable
QN
Q
msec after
RESET
dd
Reset
rises
- 24 -
delay should exceed the time period it takes V
a valid operating voltage.
Note 1: The external Power-On Reset circuit is required
only if V
charge the capacitor quickly when V
Note 2: R < 40 k
voltage drop across R does not violate the device electri-
cal specifications.
Note 3: R1 = 100
into MCLR from external capacitor C. This helps prevent
MCLR pin breakdown due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
Figure 12-2. Time-Out Sequence on Power-Up
drt_time_out
drt_time_out
Figure 12-3. Time-out Sequence on Power-up
Figure 12-4. Time-out Sequence on Power-up
drt_time_out
(MCLR tied to V
dd
RESET
RESET
RESET
(MCLR tied to V
MCLR
MCLR
MCLR
power-up is too slow. The diode D helps dis-
POR
POR
POR
V
V
V
dd
dd
dd
(MCLR not tied to V
Tdrt
Tdrt
is recommended to make sure that
to 1k
dd
dd
): Fast V
will limit any current flowing
): Slow Rise Time
V1
dd
Tdrt
dd
dd
Rise Time
powers down.
)
www.scenix.com
dd
to reach