AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 95

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

14.6
PIO Base Address: 0xFFFF0000 (Code Label PIO_BASE)
Table 14-2.
Notes:
6174B–ATARM–07-Nov-05
Offset
0x0C
0x1C
0x2C
0x3C
0x4C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
0x40
0x44
0x48
PIO User Interface
1. The reset value of this register depends on the level of the external pins at reset.
2. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes have
occurred on any pins between the reset and the read.
PIO Controller Memory Map
Register
PIO Enable Register
PIO Disable Register
PIO Status Register
Reserved
Output Enable Register
Output Disable Register
Output Status Register
Reserved
Input Filter Enable Register
Input Filter Disable Register
Input Filter Status Register
Reserved
Set Output Data Register
Clear Output Data Register
Output Data Status Register
Pin Data Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Interrupt Status Register
(2)
(1)
PIO_SODR
PIO_CODR
PIO_ODSR
PIO_PDSR
PIO_ODR
PIO_IFER
PIO_IFDR
PIO_IFSR
PIO_PDR
PIO_OER
PIO_OSR
PIO_PER
PIO_PSR
PIO_IMR
AT91FR40162S Preliminary
PIO_IDR
PIO_IER
PIO_ISR
Name
–
–
–
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Write-only
Write-only
Read-only
Read-only
Access
–
–
–
(see
0x01FFFFFF
Reset State
Table
(1)
(2)
–
–
–
–
–
0
–
–
–
0
–
–
–
0
–
–
0
14-1)
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