AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 181

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

20. AC Characteristics
20.1
20.1.1
6174B–ATARM–07-Nov-05
Applicable Conditions and Derating Data
Conditions and Timing Results
The delays are given as typical values in the following conditions:
The minimum and maximum values given in the AC characteristic tables of this datasheet take
into account the process variation and the design.
In order to obtain the timing for other conditions, the following equation should be used:
Where:
The input delays are given as typical values.
Note:
• V
• V
• Ambient Temperature = 25 C
• Load Capacitance = 0 pF
• The output level change detection is 0.5 x V
• The input level is 0.8V for a low-level detection and is 2.0V for a high level detection.
•
•
• t
•
• C
•
t
capacitance of 0 pF.
pins given in Min and Max values in this datasheet.
DATASHEET
=
T
VDDCORE
VDDIO
CSIGNAL
DDIO
DDCORE
SIGNAL
is the derating factor in temperature given in
T
1. The user must take into account the package capacitance load contribution (C
= 3.0V
is the derating factor for the I/O Power Supply given in
is the capacitance load on the considered output pin.
Table 19-2 on page
is the load derating factor depending on the capacitance load on the related output
= 1.8V
is the derating factor for the Core Power Supply given in
is the minimum or maximum timing value given in this datasheet for a load
VDDCORE
t
DATASHEET
176.
+
AT91FR40162S Preliminary
VDDIO
DDIO
Figure 20-1 on page
C
SIGNAL
(1)
Figure 20-3 on page
Figure 20-2 on page
CSIGNAL
182.
IN
) described in
183.
182.
181