AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 125

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

17.7
17.8
6174B–ATARM–07-Nov-05
Peripheral Data Controller
Interrupt Generation
Each USART channel is closely connected to a corresponding Peripheral Data Controller chan-
nel. One is dedicated to the receiver. The other is dedicated to the transmitter.
Note:
The PDC channel is programmed using US_TPR (Transmit Pointer) and US_TCR (Transmit
Counter) for the transmitter and US_RPR (Receive Pointer) and US_RCR (Receive Counter) for
the receiver. The status of the PDC is given in US_CSR by the ENDTX bit for the transmitter and
by the ENDRX bit for the receiver.
The pointer registers (US_TPR and US_RPR) are used to store the address of the transmit or
receive buffers. The counter registers (US_TCR and US_RCR) are used to store the size of
these buffers.
The receiver data transfer is triggered by the RXRDY bit and the transmitter data transfer is trig-
gered by TXRDY. When a transfer is performed, the counter is decremented and the pointer is
incremented. When the counter reaches 0, the status bit is set (ENDRX for the receiver, ENDTX
for the transmitter in US_CSR) which can be programmed to generate an interrupt. Transfers
are then disabled until a new non-zero counter value is programmed.
Each status bit in US_CSR has a corresponding bit in US_IER (Interrupt Enable) and US_IDR
(Interrupt Disable) which controls the generation of interrupts by asserting the USART interrupt
line connected to the Advanced Interrupt Controller. US_IMR (Interrupt Mask Register) indicates
the status of the corresponding bits.
When a bit is set in US_CSR and the same bit is set in US_IMR, the interrupt line is asserted.
The PDC is disabled if 9-bit character length is selected (MODE9 = 1) in US_MR.
AT91FR40162S Preliminary
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