AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 74
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AT91FR40162S-CJ
Manufacturer Part Number
AT91FR40162S-CJ
Description
IC ARM MCU FLASH 1K 121BGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91FR40162S-CJ.pdf
(210 pages)
Specifications of AT91FR40162S-CJ
Core Processor
ARM7
Core Size
16/32-Bit
Speed
75MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
WDT
Number Of I /o
32
Program Memory Size
2MB (1M x 16)
Program Memory Type
FLASH
Ram Size
256K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
121-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91FR40162S-CJ
Manufacturer:
ATMEL
Quantity:
455
- Current page: 74 of 210
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13. AIC: Advanced Interrupt Controller
13.1
Figure 13-1. Advanced Interrupt Controller Block Diagram
Note:
74
Block Diagram
After a hardware reset, the AIC pins are controlled by the PIO Controller. They must be configured to be controlled by the
peripheral before being used.
External Interrupt Sources
Internal Interrupt Sources
AT91FR40162S Preliminary
Advanced Peripheral
FIQ Source
Bus (APB)
The AT91FR40162S has an 8-level priority, individually maskable, vectored interrupt controller.
This feature substantially reduces the software and real-time overhead in handling internal and
external interrupts.
The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard
interrupt request) inputs of the ARM7TDMI processor. The processor’s NFIQ line can only be
asserted by the external fast interrupt request input: FIQ. The NIRQ line can be asserted by the
interrupts generated by the on-chip peripherals and the external interrupt request lines: IRQ0 to
IRQ2.
The 8-level priority encoder allows the customer to define the priority between the different NIRQ
interrupt sources.
Internal sources are programmed to be level sensitive or edge triggered. External sources can
be programmed to be positive or negative edge triggered or high- or low-level sensitive.
The interrupt sources are listed in
Table 13-3 on page
Memorization
Memorization
Control
Logic
82.
Table 13-1 on page 75
Controller
Priority
Manager
Manager
NFIQ
NIRQ
and the AIC programmable registers in
NIRQ
NFIQ
ARM7TDMI
6174B–ATARM–07-Nov-05
Core
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