DSPIC30F6011T-20I/PF Microchip Technology, DSPIC30F6011T-20I/PF Datasheet - Page 62
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DSPIC30F6011T-20I/PF
Manufacturer Part Number
DSPIC30F6011T-20I/PF
Description
IC DSPIC MCU/DSP 132K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F5011T-20IPT.pdf
(34 pages)
3.DSPIC30F6010T-20IPF.pdf
(6 pages)
4.DSPIC30F6011T-20IPF.pdf
(12 pages)
5.DSPIC30F6011T-20IPF.pdf
(226 pages)
Specifications of DSPIC30F6011T-20I/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
132KB (44K x 24)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F6011T20IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6011T-20I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F5011T-20IPT PDF datasheet #2
- DSPIC30F6010T-20IPF PDF datasheet #3
- DSPIC30F6011T-20IPF PDF datasheet #4
- DSPIC30F6011T-20IPF PDF datasheet #5
- Current page: 62 of 226
- Download datasheet (6Mb)
dsPIC30F6011/6012/6013/6014
7.3.2
To write a block of data EEPROM, write to all sixteen
latches first, then set the NVMCON register and
program the block.
EXAMPLE 7-5:
DS70117E-page 60
MOV
MOV
MOV
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
MOV
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
WRITING A BLOCK OF DATA
EEPROM
#5
#LOW_ADDR_WORD,W0
#HIGH_ADDR_WORD,W1
W1
#data1,W2
W2
#data2,W2
W2
#data3,W2
W2
#data4,W2
W2
#data5,W2
W2
#data6,W2
W2
#data7,W2
W2
#data8,W2
W2
#data9,W2
W2
#data10,W2
W2
#data11,W2
W2
#data12,W2
W2
#data13,W2
W2
#data14,W2
W2
#data15,W2
W2
#data16,W2
W2
#0x400A,W0
W0
#0x55,W0
W0
#0xAA,W1
W1
NVMCON,#WR
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
DATA EEPROM BLOCK WRITE
TBLPAG
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
NVMCON
NVMKEY
NVMKEY
; Init pointer
; Get 1st data
; write data
; Get 2nd data
; write data
; Get 3rd data
; write data
; Get 4th data
; write data
; Get 5th data
; write data
; Get 6th data
; write data
; Get 7th data
; write data
; Get 8th data
; write data
; Get 9th data
; write data
; Get 10th data
; write data
; Get 11th data
; write data
; Get 12th data
; write data
; Get 13th data
; write data
; Get 14th data
; write data
; Get 15th data
; write data
; Get 16th data
; write data. The NVMADR captures last table access address.
; Select data EEPROM for multi word op
; Operate Key to allow program operation
; Block all interrupts with priority <7 for
; next 5 instructions
; Write the 0x55 key
; Write the 0xAA key
; Start write cycle
Preliminary
2004 Microchip Technology Inc.
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