DSPIC30F6011T-20I/PF Microchip Technology, DSPIC30F6011T-20I/PF Datasheet - Page 129
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DSPIC30F6011T-20I/PF
Manufacturer Part Number
DSPIC30F6011T-20I/PF
Description
IC DSPIC MCU/DSP 132K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F5011T-20IPT.pdf
(34 pages)
3.DSPIC30F6010T-20IPF.pdf
(6 pages)
4.DSPIC30F6011T-20IPF.pdf
(12 pages)
5.DSPIC30F6011T-20IPF.pdf
(226 pages)
Specifications of DSPIC30F6011T-20I/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
132KB (44K x 24)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F6011T20IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6011T-20I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F5011T-20IPT PDF datasheet #2
- DSPIC30F6010T-20IPF PDF datasheet #3
- DSPIC30F6011T-20IPF PDF datasheet #4
- DSPIC30F6011T-20IPF PDF datasheet #5
- Current page: 129 of 226
- Download datasheet (6Mb)
18.3.7
The DCI module has a dedicated 12-bit time base that
produces the bit clock. The bit clock rate (period) is set
by writing a non-zero 12-bit value to the BCG<11:0>
control bits in the DCICON1 SFR.
When the BCG<11:0> bits are set to zero, the bit clock
will be disabled. If the BCG<11:0> bits are set to a non-
zero value, the bit clock generator is enabled. These
bits should be set to ‘0’ and the CSCKD bit set to ‘1’ if
the serial clock for the DCI is received from an external
device.
The formula for the bit clock frequency is given in
Equation 18-2.
TABLE 18-1:
2004 Microchip Technology Inc.
Note 1: When the CSCK signal is applied externally (CSCKD = 1), the external clock high and low times must meet
F
S
44.1
(KHz)
12
32
48
8
2: When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the
BIT CLOCK GENERATOR
the device timing requirements.
operation of the DCI module.
DEVICE FREQUENCIES FOR COMMON CODEC CSCK FREQUENCIES
F
CSCK
256
256
32
32
64
/F
S
F
CSCK
dsPIC30F6011/6012/6013/6014
1.4112
3.072
2.048
1.024
3.072
(MHz)
(1)
Preliminary
F
OSC
5.6448
8.192
6.144
8.192
6.144
EQUATION 18-2:
The required bit clock frequency will be determined by
the system sampling rate and frame size. Typical bit
clock frequencies range from 16x to 512x the converter
sample rate depending on the data converter and the
communication protocol that is used.
To achieve bit clock frequencies associated with com-
mon audio sampling rates, the user will need to select
a crystal frequency that has an ‘even’ binary value.
Examples of such crystal frequencies are listed in
Table 18-1.
(MH
Z
)
PLL
F
16
4
8
8
8
BCK
=
BIT CLOCK FREQUENCY
2 (BCG + 1)
•
F
F
CY
11.2896
12.288
16.384
24.576
CY
8.192
(MIPS)
DS70117E-page 127
BCG
1
1
7
3
3
(2)
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