DSPIC30F6011T-20I/PF Microchip Technology, DSPIC30F6011T-20I/PF Datasheet - Page 137
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DSPIC30F6011T-20I/PF
Manufacturer Part Number
DSPIC30F6011T-20I/PF
Description
IC DSPIC MCU/DSP 132K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F5011T-20IPT.pdf
(34 pages)
3.DSPIC30F6010T-20IPF.pdf
(6 pages)
4.DSPIC30F6011T-20IPF.pdf
(12 pages)
5.DSPIC30F6011T-20IPF.pdf
(226 pages)
Specifications of DSPIC30F6011T-20I/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
132KB (44K x 24)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F6011T20IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6011T-20I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F5011T-20IPT PDF datasheet #2
- DSPIC30F6010T-20IPF PDF datasheet #3
- DSPIC30F6011T-20IPF PDF datasheet #4
- DSPIC30F6011T-20IPF PDF datasheet #5
- Current page: 137 of 226
- Download datasheet (6Mb)
19.4
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the conver-
sion trigger. The SSRC bits provide for up to 4 alternate
sources of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the con-
version trigger is under A/D clock control. The SAMC
bits select the number of A/D clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least 1 clock cycle.
Other trigger sources can come from timer modules or
external interrupts.
19.5
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing until the next sampling trigger. The ADCBUF will not
be updated with the partially completed A/D conversion
sample. That is, the ADCBUF will continue to contain
the value of the last completed conversion (or the last
value written to the ADCBUF register).
If the clearing of the ADON bit coincides with an auto-
start, the clearing has a higher priority and a new
conversion will not start.
19.6
The A/D conversion requires 14 T
A/D conversion clock is software selected, using a
six-bit counter. There are 64 possible options for T
EQUATION 19-1:
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(T
of 667 nsec (for V
Specifications section for minimum T
operating conditions.
Example 19-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
2004 Microchip Technology Inc.
AD
) must be selected to ensure a minimum T
Programming the Start of
Conversion Trigger
Aborting a Conversion
Selecting the A/D Conversion
Clock
T
AD
= T
CY
DD
* (0.5*(ADCS<5:0> + 1))
A/D CONVERSION CLOCK
= 5V). Refer to the Electrical
AD
. The source of the
AD
dsPIC30F6011/6012/6013/6014
under other
AD
AD
time
Preliminary
.
EXAMPLE 19-1:
Since,
Sampling Time = Acquisition Time + Conversion Time
Therefore,
Sampling Rate =
If SSRC<2:0> = ‘111’ and SAMC<4:0> = ‘00001’
Therefore,
Set ADCS<5:0> = 39
ADCS<5:0> = 2
Minimum T
Actual T
= ~100 kHz
= 1 T
= 15 x 667 nsec
AD
T
(15 x 667 nsec)
AD
CY
AD
= 2 •
= 39
=
=
= 667 nsec
A/D CONVERSION CLOCK
AND SAMPLING RATE
CALCULATION
= 667 nsec
= 33 .33 nsec (30 MIPS)
+ 14 T
T
33.33 nsec
1
T
T
CY
2
AD
33.33 nsec
CY
667 nsec
2
AD
(ADCS<5:0> + 1)
– 1
DS70117E-page 135
(39 + 1)
– 1
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