DSPIC30F6011T-20I/PF Microchip Technology, DSPIC30F6011T-20I/PF Datasheet
DSPIC30F6011T-20I/PF
Specifications of DSPIC30F6011T-20I/PF
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DSPIC30F6011T-20I/PF Summary of contents
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... PSV Operations Using SR In certain instructions, fetching one of the operands from Program Memory using Program Space Visibility (PSV) will corrupt specific bits in the Status Register, SR. 2004 Microchip Technology Inc. dsPIC30F6011/ 6012/6013/6014 5. Early Termination of Nested-DO loops When using two DO loops in a nested fashion, terminating the inner-level DO loop by setting the EDT(CORCON< ...
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... NC, L0 daw.b w2 bset.b SR, #C bra L1 L0:daw.b w2 L1: .... Advance Information MAC to perform unsigned integer Instruction DAW.b ;First BCD number ;Second BCD number ;If C set ;If not,do DAW and ;set the carry bit ;and exit 2004 Microchip Technology Inc. ...
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... ASM30 assembler, the application may perform a PSV access to move the source operand from Program memory to RAM register prior to performing the operations listed in Table 1. The work around for Example 2 is demonstrated in Example 3. 2004 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 ;See Note 1 ;See Note 1 ;See Note 1 ;See Note 1 ...
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... W10 ;Perform indirect ;write via W0 to ;address >= 0x900 ;read operation ;using Y-AGU ;Load address > = ;0x900 into W0 ;Load address >= ;0x900 into W10 ;Perform indirect ;write via W0 to ;address >= 0x900 ;No operation ;read operation ;using Y-AGU 2004 Microchip Technology Inc. ...
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... There are no commas between // the quoted strings in the code // segment above. 2004 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 9. Module: Interrupt Controller –Traps Catastrophic Accumulator Overflow Traps are enabled as follows: - COVTE (INTCON1<8> SATA/SATB (CORCON <7/6> carry generated out of bit 39 in the accumulator causes a catastrophic overflow of the accumulator since the sign-bit has been destroyed ...
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... On the A/D interrupt, the A/D buffer will contain conversions from the following pins in sequence: - ADCBUF0 = AN3 - ADCBUF1 = AN6 - ADCBUF2 = AN4 - ADCBUF3 = AN6 - ADCBUF4 = AN5 - ADCBUF5 = AN6 - ADCBUF6 = AN3 - ADCBUF7 = AN6 Advance Information 2004 Microchip Technology Inc. ...
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... Data loaded into TXBUF0 contains 15 MS bits of the actual 16-bit data to be transmitted, while the MS bit of TXBUF0 is cleared. 4: Not all serial clock pulses are shown in this timing diagram. 2004 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 This work around is now demonstrated by an example. ...
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... MIPS prior to the erase operation. To ensure the device is operating at less than 10 MIPS, the application may post-scale the system clock or switch to the Internal FRC oscillator. Advance Information During Row Erase pin using a voltage regulator DD greater than or equal to 4.2V, pin and ground. 2004 Microchip Technology Inc. ...
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... Code Protection Addresses in the range, 0x6000 through 0xFFFF, may not be code protected for this revision of dsPIC30F6011 and dsPIC30F6013 silicon. Work around None. 2004 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Work around For 5 volt applications, use a voltage regulator that ensures V to achieve 30 MIPS operation. ...
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... APPENDIX A: REVISION HISTORY Revision A (2/2004) Original version of the document. Revision B (4/2004) Document updated from “Confidential” to “Advance Information”. Revision C (5/2004) Added errata #3, #12, #13, #14 and #15. Revision D (11/2004) Added errata #4, #5 and #18. DS80183D-page 10 Advance Information 2004 Microchip Technology Inc. ...
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... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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