PIC18C452-E/PT Microchip Technology, PIC18C452-E/PT Datasheet - Page 61
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18C452-E/PT
Manufacturer Part Number
PIC18C452-E/PT
Description
IC MCU OTP 16KX16 A/D 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C242-ISO.pdf
(305 pages)
4.PIC18C242-ISO.pdf
(12 pages)
Specifications of PIC18C452-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC18C452E/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C452-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C242-ISO PDF datasheet #3
- PIC18C242-ISO PDF datasheet #4
- Current page: 61 of 305
- Download datasheet (6Mb)
5.2.3
The long write must be terminated by a RESET or any
interrupt.
The interrupt source must have its interrupt enable bit
set. When the source sets its interrupt flag, program-
ming will terminate. This will occur, regardless of the
settings of interrupt priority bits, the GIE/GIEH bit, or
the PIE/GIEL bit.
TABLE 5-2:
5.2.4
If a write is terminated by an unplanned event such as
loss of power, an unexpected RESET, or an interrupt
that was not disabled, the memory location just pro-
grammed should be verified and reprogrammed if
needed.
(default)
(default)
(default)
2001 Microchip Technology Inc.
GIEH
GIE/
X
X
0
0
1
0
1
INTERRUPTS
UNEXPECTED TERMINATION OF
WRITE OPERATIONS
(default)
(default)
(default)
GIEL
PIE/
X
X
0
1
0
1
0
LONG WRITE EXECUTION, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS
high priority
high priority
(default)
(default)
Priority
low
low
X
X
X
1
0
0
1
Interrupt
(default)
Enable
0
1
1
1
1
1
1
Interrupt
Flag
X
0
1
1
1
1
1
Long write continues
even if interrupt flag becomes set.
Long write continues, will resume operations
when the interrupt flag is set.
Terminates long write, executes next instruction.
Terminates long write, executes next instruction.
Interrupt flag not cleared.
Terminates long write, executes next instruction.
Interrupt flag not cleared.
Terminates long write,
branches to low priority interrupt vector.
Interrupt flag can be cleared by ISR.
Terminates long write,
branches to high priority interrupt vector.
Interrupt flag can be cleared by ISR.
Interrupt flag not cleared.
Depending on the states of interrupt priority bits, the
GIE/GIEH bit or the PIE/GIEL bit, program execution
can either be vectored to the high or low priority Inter-
rupt Service Routine (ISR), or continue execution from
where programming commenced.
In either case, the interrupt flag will not be cleared
when programming is terminated and will need to be
cleared by the software.
Action
PIC18CXX2
DS39026C-page 59
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