PIC18C452-E/PT Microchip Technology, PIC18C452-E/PT Datasheet - Page 225
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18C452-E/PT
Manufacturer Part Number
PIC18C452-E/PT
Description
IC MCU OTP 16KX16 A/D 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C242-ISO.pdf
(305 pages)
4.PIC18C242-ISO.pdf
(12 pages)
Specifications of PIC18C452-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC18C452E/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C452-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C242-ISO PDF datasheet #3
- PIC18C242-ISO PDF datasheet #4
- Current page: 225 of 305
- Download datasheet (6Mb)
SUBLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
Q Cycle Activity:
2001 Microchip Technology Inc.
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
WREG
C
WREG
C
Z
N
WREG
C
WREG
C
Z
N
WREG
C
WREG
C
Z
N
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
literal ’k’
Subtract WREG from literal
[ label ] SUBLW k
0
k – (WREG)
N,OV, C, DC, Z
WREG is subtracted from the
eight-bit literal 'k'. The result is
placed in WREG.
1
1
SUBLW
SUBLW
SUBLW
Read
Q2
0000
1
?
1
1
0
0
2
?
0
1
1
0
3
?
FF
0
0
1
k
255
; (2’s complement)
; result is negative
0x02
0x02
0x02
; result is positive
1000
; result is zero
Process
Data
Q3
WREG
kkkk
Write to
WREG
Q4
kkkk
SUBWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
WREG
C
REG
WREG
C
Z
N
REG
WREG
C
REG
WREG
C
Z
N
REG
WREG
C
REG
WREG
C
Z
N
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ’f’
Subtract WREG from f
[ label ] SUBWF
0
d
a
(f) – (WREG)
N,OV, C, DC, Z
Subtract WREG from register 'f'
(2’s complement method). If 'd' is
0, the result is stored in WREG. If
'd' is 1, the result is stored back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ’a’ is
1, then the bank will be selected
as per the BSR value (default).
1
1
SUBWF
SUBWF
SUBWF
Read
Q2
0101
3
2
?
1
2
1
0
0
2
2
?
2
0
1
1
0
1
2
?
FFh
2
0
0
1
f
PIC18CXX2
[0,1]
[0,1]
255
; result is positive
; result is zero
;(2’s complement)
; result is negative
REG, 1, 0
REG, 0, 0
REG, 1, 0
11da
Process
Data
Q3
DS39026C-page 223
dest
ffff
f [,d [,a]
destination
Write to
Q4
ffff
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