PIC18C452-E/PT Microchip Technology, PIC18C452-E/PT Datasheet - Page 204
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18C452-E/PT
Manufacturer Part Number
PIC18C452-E/PT
Description
IC MCU OTP 16KX16 A/D 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C242-ISO.pdf
(305 pages)
4.PIC18C242-ISO.pdf
(12 pages)
Specifications of PIC18C452-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC18C452E/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C452-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C242-ISO PDF datasheet #3
- PIC18C242-ISO PDF datasheet #4
- Current page: 204 of 305
- Download datasheet (6Mb)
PIC18CXX2
BZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39026C-page 202
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Zero
If Zero
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Zero
[ label ] BZ
-128
if Zero bit is ’1’
(PC) + 2 + 2n
None
If the Zero bit is ’1’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
Q2
’n’
’n’
=
=
=
=
n
address (HERE)
1;
address (Jump)
0;
address (HERE+2)
127
0000
operation
BZ
Process
Process
n
Data
Data
No
Q3
Q3
PC
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
CALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
PC
PC
TOS =
WS
BSRS=
STATUSS = STATUS
No
Q1
=
=
=
Read literal
Address(HERE)
Address(THERE)
Address (HERE + 4)
WREG
BSR
operation
’k’<7:0>,
Subroutine Call
[ label ] CALL k [,s]
0
s
(PC) + 4
k
if s = 1
(WREG)
(STATUS)
(BSR)
None
Subroutine call of entire 2M byte
memory range. First, return
address (PC+ 4) is pushed onto the
return stack. If ’s’ = 1, the W,
STATUS and BSR registers are
also pushed into their respective
shadow registers, WS, STATUSS
and BSRS. If 's' = 0, no update
occurs (default). Then the 20-bit
value ’k’ is loaded into PC<20:1>.
CALL is a two-cycle instruction.
2
2
HERE
1110
1111
No
Q2
k
[0,1]
PC<20:1>,
2001 Microchip Technology Inc.
1048575
BSRS
k
110s
Push PC to
CALL
19
TOS,
WS,
operation
kkk
STATUSS,
stack
No
Q3
THERE,1
k
kkkk
7
kkk
Write to PC
Read literal
’k’<19:8>,
operation
Q4
No
kkkk
kkkk
0
8
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