ATMEGA161-8PI Atmel, ATMEGA161-8PI Datasheet - Page 114

• Manufacturer Part Number: ATMEGA161-8PI
• Description: IC AVR MCU 16K 8MHZ IND 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA1618PI

Store Program Memory
Control Register – SPMCR
114
ATmega161(L)
The Store Program Memory Control Register contains the control bits needed to control
the programming of the Flash from internal code execution.
• Bits 7..4
These bits are reserved bits in the ATmega161 and always read as zero.
• Bit 3
If this bit is set at the same time as SPMEN, the next SPM instruction within four clock
cycles sets Boot Lock bits according to the data in R0. The data in R1 and the address
in the Z-pointer are ignored. The BLBSET bit will auto-clear upon completion of Lock bit
set, or if no SPM instruction is executed within four clock cycles. The CPU is halted dur-
ing Lock bit setting. Only a chip erase can clear the Lock bits.
An LPM instruction within four cycles after BLBSET and SPMEN are set in the SPMCR
Register will put either the Lock bits or the Fuse bits (depending od the Z0 in the Z-
pointer) into the destination register. See “Reading the Fuse and Lock bits from Soft-
ware” for details.
• Bit 2
If this bit is set at the same time as SPMEN, the next SPM instruction within four clock
cycles executes page write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored.
The PGWRT bit will auto-clear upon completion of a page write or if no SPM instruction
is executed within four clock cycles. The CPU is halted during the entire page write
operation.
• Bit 1
If this bit is set at the same time as SPMEN, the next SPM instruction within four clock
cycles executes a page erase. The page address is taken from the high part of the Z-
pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon comple-
tion of a page erase or if no SPM instruction is executed within four clock cycles. The
CPU is halted during the entire page erase operation.
• Bit 0
This bit enables the SPM instruction for the next four clock cycles. If set together with
either BLBSET, PGWRT or PGERS, the following SPM instruction will have a special
meaning (see description above). If only SPMEN is set, the following SPM instruction
will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer.
The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of
an SPM instruction or if no SPM instruction is executed within four clock cycles.
Writing any combination other than “1001”, “0101”, “0011” or “0001” in the lower four
bits, or writing to the I/O Register when any bits are set, will have no effect.
Bit
$37 ($57)
Read/Write
Initial Value
–
–
–
–
BLBSET: Boot Lock Bit Set
PGWRT: Page Write
PGERS: Page Erase
SPMEN: Store Program Memory Enable
–
Res: Reserved Bits
R
7
–
0
R
6
–
0
R
5
0
R
4
0
BLBSET
R/W
3
0
PGWRT
R/W
2
0
PGERS
R/W
1
0
SPMEN
R/W
1228D–AVR–02/07
0
0
SPMCR