ATMEGA161-8PI Atmel, ATMEGA161-8PI Datasheet
ATMEGA161-8PI
Specifications of ATMEGA161-8PI
Related parts for ATMEGA161-8PI
ATMEGA161-8PI Summary of contents
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... ATmega161L – 4.0V - 5.5V for the ATmega161 • Speed Grades – MHz for the ATmega161L – MHz for the ATmega161 • Commercial and Industrial Temperature Ranges Disclaimer Typical values contained in this data sheet are based on simulations and characteriza- tion of other AVR microcontrollers manufactured on the same process technology ...
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... Pin Configuration ATmega161(L) 2 PDIP (OC0/T0) PB0 1 (OC2/T1) PB1 2 (RXD1/AIN0) PB2 3 (TXD1/AIN1) PB3 4 (SS) PB4 5 (MOSI) PB5 6 (MISO) PB6 7 (SCK) PB7 8 RESET 9 (RXD0) PD0 10 (TXD0) PD1 11 (INT0) PD2 12 (INT1) PD3 13 (TOSC1) PD4 14 (OC1A/TOSC2) PD5 15 (WR) PD6 16 (RD) PD7 17 XTAL2 18 XTAL1 19 GND 20 TQFP ...
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... In-System Programmable Flash on a monolithic chip, the Atmel ATmega161 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. The ATmega161 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Cir- cuit Emulators and evaluation kits. ...
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... Block Diagram ATmega161(L) 4 Figure 1. The ATmega161 Block Diagram PA0-PA7 VCC PORTA DRIVERS GND DATA REGISTER DATA DIR. PORTA REG. PORTA PROGRAM STACK COUNTER POINTER PROGRAM SRAM FLASH INSTRUCTION GENERAL REGISTER PURPOSE REGISTERS X INSTRUCTION Y DECODER Z CONTROL ALU LINES STATUS REGISTER PROGRAMMING SPI ...
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... The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega161 as listed on page 107. Reset input. A low level on this pin for more than 500 ns will generate a Reset, even if the clock is not running ...
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... Crystal Oscillator ATmega161(L) 6 XTAL1 and XTAL2 are input and output, respectively inverting amplifier that can be configured for use as an on-chip Oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3. ...
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... These added function registers are the 16-bit X-register, Y-register and Z-register. The ALU supports arithmetic and logic functions between registers or between a con- stant and a register. Single register operations are also executed in the ALU. Figure 4 shows the ATmega161 AVR RISC microcontroller architecture. Figure 4. The ATmega161 AVR RISC Architecture Program ...
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... ATmega161( addition to the register operation, the conventional Memory Addressing modes can be used on the Register File. This is enabled by the fact that the Register File is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations. The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, and other I/O functions ...
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... Status Register. All the different interrupts have a sepa- rate Interrupt Vector in the Interrupt Vector table at the beginning of the Program memory. The different interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. ATmega161(L) Data Memory $0000 $000 32 Gen ...
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... The General Purpose Register File The X-register, Y-register and Z-register ATmega161(L) 10 Figure 6 shows the structure of the 32 general purpose working registers in the CPU. Figure 6. AVR CPU General Purpose Working Registers 7 General Purpose Working Registers All the register operating instructions in the instruction set have direct and single cycle access to all registers ...
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... See page 110 for a detailed description of Flash data downloading. See page 13 for the different Program Memory Addressing modes. The ATmega161 contains 512 bytes of data EEPROM memory organized as a sep- arate data space in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles per location ...
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... SRAM Data Memory ATmega161(L) 12 Figure 8 shows how the ATmega161 SRAM memory is organized. Figure 8. SRAM Organization Register File … R29 R30 R31 I/O Registers $00 $01 $02 … $3D $3E $3F The lower 1120 Data memory locations address the Register File, the I/O memory and the internal data SRAM. The first 96 locations address the Register File and I/O memory and the next 1K locations address the internal data SRAM ...
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... X, Y, and Z are decremented and incremented. The 32 general purpose working registers, 64 I/O Registers and the 1K byte of internal data SRAM in the ATmega161 are all accessible through all these Addressing modes. See the next section for a detailed description of the different Addressing modes. ...
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... I/O Direct Data Direct ATmega161(L) 14 Operands are contained in registers r (Rr) and d (Rd). The result is stored in register d (Rd). Figure 11. I/O Direct Addressing Operand address is contained in six bits of the instruction word the destination or Source Register Address. Figure 12. Direct Data Addressing LSBs 15 A 16-bit data address is contained in the 16 LSBs of a two-word instruction. Rd/Rr spec- ify the destination or source register ...
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... Figure 14. Data Indirect Addressing REGISTER Operand address is the contents of the X-, Y-, or Z-register. Figure 15. Data Indirect Addressing with Pre-decrement REGISTER The X-, Y-, or Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or Z-register. ATmega161(L) Data Space Data Space 0 Data Space 0 ...
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... Data Indirect with Post- increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL ATmega161(L) 16 Figure 16. Data Indirect Addressing with Post-increment REGISTER The X-, Y-, or Z-register is incremented after the operation. Operand address is the con- tents of the X-, Y-, or Z-register prior to incrementing. ...
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... Figure 21 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks and functions per power unit. ATmega161(L) PROGRAM MEMORY PROGRAM MEMORY 16 ...
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... ATmega161(L) 18 Figure 21. The Parallel Instruction Fetches and Instruction Executions T1 System Clock Ø 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 22 shows the internal timing concept for the Register File single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destination register ...
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... Memory 1228D–AVR–02/07 The I/O space definition of the ATmega161 is shown in Table 1. (1) Table 1. ATmega161 I/O Space I/O Address (SRAM Address) Name $3F($5F) SREG $3E ($5E) SPH $3D ($5D) SPL $3B ($5B) GIMSK $3A ($5A) GIFR $39 ($59) TIMSK $38 ($58) TIFR $37 ($57) SPMCR $36 ($56) EMCUCR ...
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... ATmega161(L) 20 (1) Table 1. ATmega161 I/O Space I/O Address (SRAM Address) Name Function $1C ($3C) EECR EEPROM Control Register $1B($3B) PORTA Data Register, Port A $1A ($3A) DDRA Data Direction Register, Port A $19 ($39) PINA Input Pins, Port A $18 ($38) PORTB Data Register, Port B $17 ($37) DDRB Data Direction Register, Port B ...
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... Status Register – SREG 1228D–AVR–02/07 All ATmega161 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general pur- pose working registers and the I/O space. I/O Registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...
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... Note that the Status Register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. This must be handled by software. The ATmega161 Stack Pointer is implemented as two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the ATmega161 supports up to 64-Kbyte mem- ory, all 16 bits are used. Bit 15 ...
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... ATmega161(L) (1) Interrupt Definition External Pin, Power-on Reset and Watchdog Reset External Interrupt Request 0 External Interrupt Request 1 External Interrupt Request 2 Timer/Counter2 Compare Match Timer/Counter2 Overflow Timer/Counter1 Capture Event Timer/Counter1 Compare Match A ...
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... ATmega161(L) 24 $01a jmp $01c jmp $01e jmp $020 jmp $022 jmp $024 jmp $026 jmp $028 jmp ; $02a MAIN: ldi r16,high(RAMEND) ; Main program start $02b out SPH,r16 $02c ldi r16,low(RAMEND) $02d out SPL,r16 $02e <instr> … … … When the BOOTRST fuse is programmed, the most typical and general program setup ...
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... Reset Sources 1228D–AVR–02/07 The ATmega161 has three sources of Reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). POT • External Reset. The MCU is reset when a low level is present on the RESET pin for more than 500 ns. • ...
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... ATmega161(L) 26 Table 3. Reset Characteristics (V CC Symbol Parameter V Power-on Reset Threshold Voltage (rising) POT Power-on Reset Threshold Voltage (falling) V RESET Pin Threshold Voltage RST Note: 1. The Power-on Reset will not work unless the supply voltage has been below V (falling). ‘ (3) Table 4. Reset Delay Selections ...
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... Figure 25. MCU Start-up, RESET Tied POT VCC V RST RESET t TOUT TIME-OUT INTERNAL RESET Figure 26. MCU Start-up, RESET Controlled Externally V POT VCC RESET TIME-OUT INTERNAL RESET ATmega161(L) ). The POR is activated whenever V CC rise. The time-out period of CC decreases below detection level RST t TOUT is below CC 27 ...
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... External Reset Watchdog Reset ATmega161( External Reset is generated by a low level on the RESET pin. Reset pulses longer than 500 ns will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset. When the applied signal reaches the Reset ...
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... Bits 7..4 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and always read as zero. • Bit 3 WDRF: Watchdog Reset Flag – This bit is set if a Watchdog Reset occurs. The bit is cleared by a Power-on Reset or by writing a logical “0” to the Flag. ...
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... Interrupt Response Time General Interrupt Mask Register – GIMSK ATmega161(L) 30 Note that the Status Register is not automatically stored when entering an interrupt rou- tine or restored when returning from an interrupt routine. This must be handled by software. The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum ...
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... General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK 1228D–AVR–02/07 • Bits 4..0 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and always read as zero. Bit $3A ($5A) INTF1 INTF0 INTF2 Read/Write R/W R/W ...
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... ATmega161(L) 32 • Bit 5 OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable – When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at Vector $010) is executed if a Compare B Match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register (TIFR). • ...
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... The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 (Output Compare Register 2). OCF2 is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, OCF2 is cleared by writing a logical “1” to the Flag. When the I-bit in SREG and OCIE2 (Timer/Counter2 ATmega161( ...
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... External Interrupts MCU Control Register – MCUCR ATmega161(L) 34 Compare match InterruptA Enable) and the OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed. • Bit 1 TOV0: Timer/Counter0 Overflow Flag – The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, TOV0 is cleared by writing a logical “ ...
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... Table 8. Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request Any logical change on INT0 generates an interrupt request The falling edge of INT0 generates an interrupt request The rising edge of INT0 generates an interrupt request. ATmega161(L) Sleep Mode Idle Reserved Power-down Power-save 35 ...
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... SRL2, SRL1, SRL0: External SRAM Limit – possible to configure different wait states for different external memory addresses in ATmega161. The SRL2 - SRL0 bits are used to define at which address the different wait states will be configured. See “Interface to External Memory” on page 84 for a detailed description. ...
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... TIMSK and the global interrupt enable bit in SREG is set. If the asynchronous timer is not clocked asynchronously, Power-down mode is recom- mended instead of Power-save mode because the contents of the register in the asynchronous timer should be considered undefined after wake-up in Power-save mode even if AS2 is 0. ATmega161(L) 37 ...
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... Prescalers ATmega161(L) 38 The ATmega161 provides three general purpose Timer/Counters – two 8-bit T/Cs and one 16-bit T/C. Timer/Counter2 can optionally be asynchronously clocked from an exter- nal Oscillator. This Oscillator is optimized for use with a 32.768 kHz watch crystal, enabling use of Timer/Counter2 as a Real-time Clock (RTC). Timer/Counters 0 and 1 have individual prescaling selection from the same 10-bit prescaling timer ...
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... Initial Value • Bits 7..2 – Res: Reserved Bits These bits are reserved bits in the ATmega161 and always read as zero. • Bit 1 PSR2: Prescaler Reset Timer/Counter2 – When this bit is set (one), the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect ...
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... Timer/Counters T/C0 and T/C2 ATmega161(L) 40 • Bit 0 PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 – When this bit is set (one), the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers ...
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... Timer/Counters 0 and 2 can also be used as 8-bit Pulse Width Modulators. In this mode, the Timer/Counter and the Output Compare Register serve as a glitch-free, stand-alone PWM with centered pulses. Refer to page 44 for a detailed description of this function. ATmega161(L) T/C2 COMPARE MATCH IRQ 8-BIT DATA BUS ...
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... Timer/Counter0 Control Register – TCCR0 Timer/Counter2 Control Register – TCCR2 ATmega161(L) 42 Bit $33 ($53) FOC0 PWM0 COM01 Read/Write R/W R/W R/W Initial Value Bit $27 ($47) FOC2 PWM2 COM21 Read/Write R/W R/W R/W Initial Value • Bit 7 FOC0/FOC2: Force Output Compare – Writing a logical “1” to this bit forces a change in the compare match output pin PB0 (Timer/Counter0) and PB1 (Timer/Counter2) according to the values already set in COMn1 and COMn0 ...
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... CK Oscillator clock for Timer/Counter0 and PCK2 for Timer/Counter2. If the external pin modes are used for Timer/Counter0, transitions on PB0/(T0) will clock the counter even if the pin is configured as an output. This feature can give the user software control of the counting. ATmega161(L) Description Stop, the Timer/Counter0 is stopped. CK ...
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... Timer Counter0 – TCNT0 Timer/Counter2 – TCNT2 Timer/Counter0 Output Compare Register – OCR0 Timer/Counter2 Output Compare Register – OCR2 Timer/Counters 0 and 2 in PWM Mode ATmega161(L) 44 Bit $32 ($52) MSB Read/Write R/W R/W R/W Initial Value Bit $23 ($43) MSB Read/Write R/W R/W R/W ...
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... Note that in PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location and then latched into the OCR when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR0 or OCR2 write. See Figure 33 and Figure 34 for examples. ATmega161(L) (1) Frequency TCK0/2 f ...
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... ATmega161(L) 46 Figure 33. Effects of Unsynchronized OCR Latching in Up/Down Mode Compare Value changes Synchronized OCn Latch Compare Value changes Unsynchronized OCn Latch Figure 34. Effects of Unsynchronized OCR Latching in Overflow Mode. Synchronized OCn Latch Unsynchronized OCn Latch Note (Figure 33 and Figure 34) During the time between the write and the latch operation, a read from the Output Com- pare Registers will read the contents of the temporary location ...
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... Bits 7..4 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and always read as zero. • Bit 3 AS2: Asynchronous Timer/Counter2 Mode – When this bit is cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK. If AS2 is set, the Timer/Counter2 is clocked from the TOSC1 pin. Pins PD4 and PD5 become connected to a crystal Oscillator and cannot be used as general I/O pins ...
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... Asynchronous Operation of Timer/Counter2 ATmega161(L) 48 When Timer/Counter2 operates asynchronously, some considerations must be taken: • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might get corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2. ...
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... When Timer/Counter1 is externally clocked, the external signal is synchronized with the Oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU ATmega161(L) T/C1 INPUT CAPTURE IRQ T/C1 CONTROL ...
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... Timer/Counter1 Control Register A – TCCR1A ATmega161(L) 50 clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 16-bit Timer/Counter1 features both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. Similarly, the high-prescaling opportunities make the Timer/Counter1 useful for lower speed functions or exact timing functions with infrequent actions ...
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... Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens Compare Match had occurred, but no interrupt is generated. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mode. ATmega161(L) (1) 51 ...
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... Register (ICR1) on the rising edge of the Input Capture pin (ICP). • Bits 5, 4 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and always read as zero. • Bit 3 CTC1: Clear Timer/Counter1 on Compare Match – When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match ...
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... CPU and the data of the High byte TCNT1H is placed in the TEMP Register. When the CPU reads the data in the High byte TCNT1H, the CPU receives the data in the TEMP Register. Consequently, the Low byte TCNT1L must be accessed first for a full 16-bit register read operation. ATmega161(L) Description Stop, the Timer/Counter1 is stopped. CK ...
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... Compare Register – OCR1BH AND OCR1BL Timer/Counter1 Input Capture Register – ICR1H AND ICR1L ATmega161(L) 54 The Timer/Counter1 is realized up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the writ- ten value ...
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... OCR1A, OCR1B and TCNT1 if the 9-bit PWM resolution is selected. This makes it possible for the user to perform read-modify-write operations in any of the three resolution modes and the unused bits will be treated as don’t care. ATmega161(L) PWM Resolution Timer TOP Value 8-bit ...
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... ATmega161(L) 56 Table 18. Compare1 Mode Select in PWM Mode CTC1 COM1X1 COM1X0 Effect on OCX1 Not connected Not connected Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM Not connected Not connected Cleared on compare match, set on overflow. ...
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... Timer/Counter mode. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode, i.e executed when TOV1 is set, provided that Timer Overflow Interrupt1 and global interrupts are enabled. This also applies to the Timer Output Compare1 Flags and interrupts. ATmega161(L) 1 PWM Output OC1x PWM Output OC1x ...
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... Bits 7..5 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and will always read as zero. • Bit 4 WDTOE: Watchdog Turn-off Enable – This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will not be disabled ...
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... Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the Watchdog Timer may not start counting from zero. To avoid unintentional MCU Reset, the Watchdog Timer should be disabled or reset before changing the Watchdog Timer Prescale Select. ATmega161(L) (1) Typical Time-out ...
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... X X • Bits 15..9 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and will always read as zero. • Bits 8..0 EEAR8..0: EEPROM Address – The EEPROM Address Registers (EEARH and EEARL) specify the EEPROM address in the 512-byte EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511 ...
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... Bits 7..4 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and will always read as zero. • Bit 3 EERIE: EEPROM Ready Interrupt Enable – When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled ...
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... Prevent EEPROM Corruption ATmega161(L) 62 bit. When EERE has been set, the CPU is halted for four cycles before the next instruc- tion is executed. The user should poll the EEWE bit before starting the read operation write operation is in progress when new data or address is written to the EEPROM I/O Registers, the write operation will be interrupted and the result is undefined ...
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... Serial Peripheral Interface – SPI 1228D–AVR–02/07 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega161 and peripheral devices or between several AVR devices. The ATmega161 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • ...
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... ATmega161(L) 64 The interconnection between Master and Slave CPUs with SPI is shown in Figure 41. The PB7(SCK) pin is the Clock Output in the Master mode and is the clock input in the Slave mode. Writing to the SPI Data Register of the Master CPU starts the SPI clock generator, and the data written shifts out of the PB5(MOSI) pin and into the PB5(MOSI) pin of the Slave CPU ...
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... There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 42 and Figure 43. Figure 42. SPI Transfer Format with CPHA = 0 and DORD = 0 ATmega161(L) 65 ...
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... SPI Control Register – SPCR ATmega161(L) 66 Figure 43. SPI Transfer Format with CPHA = 1 and DORD = 0 Bit $0D ($2D) SPIE SPE DORD Read/Write R/W R/W R/W Initial Value • Bit 7 SPIE: SPI Interrupt Enable – This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the global interrupt enable bit in SREG is set. • ...
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... WCOL set (one), and then by accessing the SPI Data Register. • Bits 5..1 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and will always read as zero. • Bit 0 SPI2X: Double SPI Speed Bit – When this bit is set (one), the SPI speed (SCK frequency) will be doubled when the SPI is in Master mode (see Table 23) ...
Page 68
... SPI Data Register – SPDR ATmega161(L) 68 Bit $0F ($2F) MSB Read/Write R/W R/W R/W Initial Value The SPI Data Register is a read/write register used for data transfer between the Regis- ter File and the SPI Shift Register. Writing to the register initiates data transmission. ...
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... UARTs Data Transmission 1228D–AVR–02/07 The ATmega161 features two full-duplex (separate Receive and Transmit Registers) Universal Asynchronous Receiver and Transmitters (UARTs). The main features are: • Baud Rate Generator Generates any Baud Rate • High Baud Rates at low XTAL Frequencies • ...
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... ATmega161(L) 70 • A new character has been written to UDRn before the stop bit from the previous character has been shifted out. The Shift Register is loaded when the stop bit of the character currently being transmitted has been shifted out. If the 10(11)-bit Transmit Shift Register is empty, data is transferred from UDRn to the Shift Register ...
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... Transmitter Shift Register as they are sampled. Sampling of an incoming character is shown in Figure 46. Note that the description above is not valid when the UART trans- mission speed is doubled. See “Double-speed Transmission” on page 78 for a detailed description. ATmega161(L) DATA BUS UART I/O DATA REGISTER (UDRn) ...
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... ATmega161(L) 72 Figure 46. Sampling Received Data Note: 1. This figure is not valid when the UART speed is doubled. See Transmission” on page 78 When the stop bit enters the Receiver, the majority of the three samples must be one to accept the stop bit. If two or more samples are logical “0”s, the Framing Error (FEn) Flag in the UART Control and Status Register (UCSRnA) is set ...
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... The UDRn Register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data Register is written. When reading from UDRn, the UART Receive Data Register is read. Bit $0B ($2B) RXC0 TXC0 UDRE0 Read/Write R R/W R Initial Value ATmega161( R/W R/W R/W R R/W R/W ...
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... UART1 Control and Status Registers – UCSR1A ATmega161(L) 74 Bit $02 ($22) RXC1 TXC1 UDRE1 Read/Write R R/W R Initial Value • Bit 7 RXC0/RXC1: UART Receive Complete – This bit is set (one) when a received character is transferred from the Receiver Shift Register to UDRn. The bit is set regardless of any detected framing errors. When the RXCIEn bit in UCSRnB is set, the UART Receive Complete interrupt will be executed when RXCn is set (one) ...
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... Bit 2 Res: Reserved Bit – This bit is reserved bit in the ATmega161 and will always read as zero. • Bit 1 U2X0/U2X1: Double the UART Transmission Speed – When this bit is set (one), the UART speed will be doubled. This means that a bit will be transmitted/received in 8 CPU clock periods instead of 16 CPU clock periods. For a detailed description, see “ ...
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... Baud Rate Generator ATmega161(L) 76 • Bit 2 CHR90/CHR91: 9-bit Characters – When this bit is set (one), transmitted and received characters are nine bits long, plus start and stop bits. The ninth bit is read and written by using the RXB8n and TXB8 bits in UCSRnB, respectively. The ninth data bit can be used as an extra stop bit or a parity bit. ...
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... UBR= 28800 UBR= 0.0 UBR= 15 38400 UBR= 11 0.0 UBR= 57600 UBR= 0.0 UBR= 7 76800 UBR= 5 0.0 UBR= 115200 UBR= 3 0.0 UBR= ATmega161(L) 2 MHz %Error 47 0.0 UBR= 51 0.2 UBR= 23 0.0 UBR= 25 0.2 UBR= 0.0 UBR= 0.2 UBR 0.0 UBR= 8 3.7 UBR= ...
Page 78
... UBRRn stores the eight least significant bits of the UART Baud Rate Register. The ATmega161 provides a separate UART mode that allows the user to double the communication speed. By setting the U2X bit in UART Control and Status Register UCSRnA, the UART speed will be doubled. The data reception will differ slightly from Normal mode ...
Page 79
... However, since the number of samples are reduced and the system clock might have some variance (this applies especially when using resonators recommended that the baud rate error be less than 0.5%. ATmega161( ...
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... UBR = 63 19200 UBR = 47 28800 UBR = 31 38400 UBR = 23 57600 UBR = 15 76800 UBR = 11 115200 UBR = 7 230400 UBR = 3 460800 UBR = 1 912600 UBR = 0 ATmega161( Error 1.8432 MHz 0.2 UBR = 95 0.2 UBR = 47 0.2 UBR = 23 3.7 UBR = 15 7.5 UBR = 11 7.8 UBR = 7 7.8 UBR = 5 7.8 UBR = 3 22.9 UBR = 2 84 ...
Page 81
... When this bit is set, a fixed bandgap voltage of 1.22 ± 0.05V replaces the normal input to the positive input (AIN0) of the comparator. When this bit is cleared, the normal input pin PB2 is applied to the positive input of the comparator. • Bit 5 ACO: Analog Comparator Output – ACO is directly connected to the comparator output. ATmega161( ACI ACIE ...
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... ATmega161(L) 82 • Bit 4 ACI: Analog Comparator Interrupt Flag – This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut- ing the corresponding Interrupt Handling Vector. Alternatively, ACI is cleared by writing a logical “ ...
Page 83
... Enable Signals and Start- up Time 1228D–AVR–02/07 ATmega161 features an internal voltage reference with a nominal voltage of 1.22V. This reference can be used as an input to the Analog Comparator. The voltage reference has a start-up time that may have an influence on the way it should be used. The maximum start-up time is TBD. To save power, the reference is on only when the AINBG bit in ACSR is set ...
Page 84
... MCU Control Register – MCUCR Extended MCU Control Register – EMCUCR ATmega161(L) 84 With all the features the external memory interface provides well suited to operate as an interface to memory devices such as external SRAM and Flash, and peripherals such as LCD display, A/D, D/A, etc. The control bits for the external memory interface are located in two registers, the MCU Control Register (MCUCR) and the Extended MCU Control Register (EMCUCR) ...
Page 85
... ATmega161(L) Page Limits Lower page = N/A Upper page = $0460-$FFFF Lower page = $0460-$1FFF Upper page = $2000-$FFFF Lower page = $0460-$4FFF Upper page = $4000-$FFFF Lower page = $0460-$5FFF Upper page = $6000-$FFFF Lower page = $0460-$7FFF Upper page = $8000-$FFFF ...
Page 86
... ATmega161(L) 86 Figure 49. External Memory with Page Select External Memory (0-63K x 8) Figure 50. External Data Memory Cycles without Wait State (SRWn1 = 0 and SRWn0 (1) =0) T1 System Clock Ø ALE Address [15..8] Prev. addr. XX Data/Address [7..0] Prev. data XX WR Prev. data Data/Address [7.. Note: 1. SRWn1 = SRW11 (upper page) or SRW01 (lower page), SRWn0 = SRW10 (upper page) or SRW00 (lower page) ...
Page 87
... SRWn1 = SRW11 (upper page) or SRW01 (lower page), SRWn0 = SRW10 (upper page) or SRW00 (lower page). The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal or external). The Data and Address will only change ALE is present (the next instruction accesses the RAM). ATmega161( ...
Page 88
... Using the External Memory Interface ATmega161(L) 88 The interface consists of: Port A: multiplexed low-order address bus and data bus Port C: high-order address bus The ALE pin: address latch enable The RD and WR pin: read and write strobes The external memory interface is enabled by setting the external SRAM enable bit (SRE) of the MCU Control Register (MCUCR) and will override the setting of the Data Direction Registers DDRA, DDRD and DDRE ...
Page 89
... PAn is configured as an input pin. If PORTAn is set (one) when the pin is configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTAn has to be cleared (zero) or the pin has to be configured as an output pin. The ATmega161( ...
Page 90
... Port A Schematics ATmega161(L) 90 Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 29. DDAn Effects on Port A Pins DDAn PORTAn I Input 0 1 Input 1 0 Output 1 1 Output Note 7,6…0, pin number Note that all port pins are synchronized. The synchronization latch is, however, not shown in the figure ...
Page 91
... N/A N/A The Port B Input Pins address (PINB) is not a register; this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read and when reading PINB, the logical values present on the pins are read. ATmega161(L) ( ...
Page 92
... Port B as General Digital I/O Alternate Functions of Port B ATmega161(L) 92 All eight pins in Port B have equal functionality when used as digital I/O pins. PBn, general I/O pin: The DDBn bit in the DDRB Register selects the direction of this pin. If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin ...
Page 93
... Timer/Counter0 compare matches. The PB0 pin has to be configured as an output (DDB0 set [one]) to serve this function. See “8-bit Timer/Counters T/C0 and T/C2” on page 40 for further details and how to enable the output. The OC0 pin is also the output pin for the PWM mode timer function. ATmega161(L) 93 ...
Page 94
... Port B Schematics ATmega161(L) 94 Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 56. Port B Schematic Diagram (Pins PB0 and PB1) PBn WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB n: 0,1 ...
Page 95
... Figure 58. Port B Schematic Diagram (Pin PB3) MOS PULL- UP PB3 WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB TXD1: UART1 TRANSMIT DATA TXEN1: UART1 TRANSMIT ENABLE AIN1: ANALOG COMPARATOR NEGATIVE INPUT ATmega161(L) RD RESET Q D DDB2 C WD RESET Q D PORTB2 RXEN1 RXD1 AIN0 RD RESET ...
Page 96
... ATmega161(L) 96 Figure 59. Port B Schematic Diagram (Pin PB4) MOS PULL- UP PB4 WP: WRITE PORTB WRITE DDRB WD: RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB SPI MASTER ENABLE MSTR: SPE: SPI ENABLE Figure 60. Port B Schematic Diagram (Pin PB5) MOS PULL- UP PB5 WP: WRITE PORTB ...
Page 97
... MASTER SELECT MSTR Figure 62. Port B Schematic Diagram (Pin PB7) MOS PULL- UP PB7 WP: WRITE PORTB WD: WRITE DDRB READ PORTB LATCH RL: READ PORTB PIN RP: READ DDRB RD: SPI ENABLE SPE: MASTER SELECT MSTR ATmega161(L) RD RESET DDB6 C WD RESET PORTB6 MSTR SPE SPI SLAVE OUT ...
Page 98
... DDRC Port C Input Pins Address – PINC Port C as General Digital I/O ATmega161(L) 98 Port 8-bit bi-directional I/O port. Three I/O memory address locations are allocated for the Port C, one each for the Data Register – PORTC, $15($35), Data Direction Register – DDRC, $14($34) and the Port C Input Pins – ...
Page 99
... Output Note 6,…0, pin number Note that all port pins are synchronized. The synchronization latch is, however, not shown in the figure. Figure 63. Port C Schematic Diagram (Pins PC0 - PC7) ATmega161(L) (1) Pull-up Comment No Tri-state (high-Z) Yes PCn will source current if ext. pulled low ...
Page 100
... DDRD Port D Input Pins Address – PIND Port D as General Digital I/O ATmega161(L) 100 Port 8-bit bi-directional I/O port with internal pull-up resistors. Three I/O address locations are allocated for the Port D, one each for the Data Register – PORTD, $12($32), Data Direction Register – DDRD, $11($31) and the Port D Input Pins – ...
Page 101
... Receive Data (Data input pin for the UART0). When the UART Receiver is enabled, this pin is configured as an input regardless of the value of DDRD0. When the UART0 forces this pin input, a logical “1” in PORTD0 will turn on the internal pull-up. ATmega161(L) (1) Pull-up Comment ...
Page 102
... Port D Schematics ATmega161(L) 102 Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 64. Port D Schematic Diagram (Pin PD0) MOS PULL- UP PD0 WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD ...
Page 103
... READ PORTD PIN RD: READ DDRD Figure 67. Port D Schematic Diagram (Pin PD4) MOS PULL- UP PD4 WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD AS2: ASYNCH SELECT T/C2 ATmega161(L) RD RESET DDD4 C WD RESET PORTD4 AS2 T/C2 OSC AMP INPUT 103 ...
Page 104
... ATmega161(L) 104 Figure 68. Port D Schematic Diagram (Pin PD5) WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD AS2 ASYNCH SELECT T/C2 Figure 69. Port D Schematic Diagram (Pin PD6) WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: ...
Page 105
... Figure 70. Port D Schematic Diagram (Pin PD7) WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD RE: READ ENABLE SRE: EXTERNAL SRAM ENABLE ATmega161(L) 105 ...
Page 106
... DDRE Port E Input Pins Address – PINE Port E as General Digital I/O ATmega161(L) 106 Port 3-bit bi-directional I/O port with internal pull-up resistors. Three I/O address locations are allocated for the Port E, one each for the Data Register – PORTE, $07($27), Data Direction Register – DDRE, $06($26) and the Port E Input Pins – ...
Page 107
... ICP, Input Capture pin: The PE0 pin can serve as the Input Capture source for Timer/Counter 1. See page 54 for a detailed description. INT2, External Interrupt source 2: The PE0 pin can serve as an external interrupt source to the MCU. See “Extended MCU Control Register – EMCUCR” on page 36 for further details. ATmega161(L) (1) Pull-up Comment No ...
Page 108
... Port E Schematics ATmega161(L) 108 Figure 71. Port E Schematic Diagram (Pin PE0) MOS PULL- UP PE0 WP: WRITE PORTE WD: WRITE DDRE RL: READ PORTE LATCH RP: READ PORTE PIN RD: READ DDRE ACIC: COMPARATOR IC ENABLE ACO: COMPARATOR OUTPUT ISC2 Figure 72. Port E Schematic Diagram (Pin PE1) MOS PULL- UP PE1 ...
Page 109
... Figure 73. Port E Schematic Diagram (Pin PE2) PE2 WP: WRITE PORTE WD: WRITE DDRE RL: READ PORTE LATCH RP: READ PORTE PIN RD: READ DDRE ATmega161(L) DDE2 PORTE2 COM1B0 COM1B1 COMP. MATCH 1B PWM10 PWM11 FOC1B 109 ...
Page 110
... The Store Program Memory (SPM) instruction can access the entire Flash, but it can only be executed from the Boot Loader Flash section Boot Loader capability is needed, the entire Flash is available for application code. The ATmega161 has two sep- arate sets of Boot Lock bits that can be set independently. This gives the user a unique flexibility to select different levels of protection ...
Page 111
... Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface. The BOOTRST fuse can also be locked by pro- gramming LB1. When LB1 is programmed it is not possible to change the BOOTRST fuse unless a Chip Erase command is performed first. ATmega161(L) Protection No restrictions for SPM, LPM accessing Application Code section SPM is not allowed to write to the Application Code section ...
Page 112
... Capabilities of the Boot Loader Self-programming the Flash Setting the Boot Loader Lock bits by SPM Performing Page Erase by SPM ATmega161(L) 112 Table 39. Boot Reset Fuse, BOOTRST BOOTRST Reset Address 1 Reset Vector = Application Reset (address $0000) 0 Reset Vector = Boot Loader Reset (address $1E00) Note: 1. “ ...
Page 113
... Accidental writing into Flash program by the SPM instruction is prevented by setting up an “SPM enable time window”. All accesses are executed by first setting I/O bits, and then by executing SPM within four clock cycles. The I/O Register that controls the SPM accesses is defined below. ATmega161(L) set up for next erase 12 11 ...
Page 114
... Bits 7..4 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and always read as zero. • Bit 3 BLBSET: Boot Lock Bit Set – If this bit is set at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits according to the data in R0 ...
Page 115
... LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the Fuse bits can be read in the destination register as shown below. Bit – BOOTRST SPIEN Fuse and Lock bits that are programmed will be read as zero. ATmega161( BLB11 BLB02 BLB01 LB2 4 ...
Page 116
... Fuse bits ATmega161(L) 116 The ATmega161 MCU provides six Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 40. The Lock bits can only be erased to “1” with the Chip Erase command. Table 40. Lock Bit Protection Modes ...
Page 117
... ATmega161 inside the user’s system. The Program memory array on the ATmega161 is organized as 128 pages of 128 bytes each. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously in either Program- ming mode ...
Page 118
... EEPROM Data memory, Lock bits and Fuse bits in the ATmega161. Pulses are assumed least 500 ns unless otherwise noted. In this section, some pins of the ATmega161 are referenced by signal names describing their functionality during parallel programming (see Figure 75 and Table 42). Pins not described in the following table are referenced by pin name. ...
Page 119
... Set BS1 to “0”. 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 5. Wait until RDY/BSY goes high before loading a new command. ATmega161(L) I/O Function I Program Memory Page Load ...
Page 120
... Programming the Flash ATmega161(L) 120 The Flash is organized as 128 pages of 128 bytes each. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “ ...
Page 121
... Figure 76. Programming the Flash Waveforms DATA $10 ADDR. LOW XA1 XA2 BS1 XTAL1 WR RDY/BSY +12V RESET OE BS2 PAGEL Figure 77. Programming the Flash Waveforms (Continued) DATA DATA HIGH XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 ATmega161(L) ADDR. HIGH DATA LOW 121 ...
Page 122
... Programming the EEPROM ATmega161(L) 122 The programming algorithm for the EEPROM Data memory is as follows (refer to “Pro- gramming the Flash” for details on command, address and data loading Load Command “0001 0001” Load Address High Byte ($00 - $01 Load Address Low Byte ($00 - $FF) 4 ...
Page 123
... Bit 3 = Boot Lock Bit02 Bit 2 = Boot Lock Bit01 Bit 1 = Lock Bit2 Bit 0 = Lock Bit1 Bits “1”. These bits are reserved and should be left unprogrammed (“1”). 3. L: Write Data Low Byte. The Lock bits can only be cleared by executing Chip Erase. ATmega161(L) 123 ...
Page 124
... Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics ATmega161(L) 124 The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 120 for details on command loading Load Command “0000 0100”. ...
Page 125
... Either an external system clock is supplied at pin XTAL1 or a crystal needs to be con- nected across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 XTAL1 clock cycles High: > 2 XTAL1 clock cycles ATmega161(L) = 25°C ± 10 Min Typ 11 ...
Page 126
... Data Polling Flash ATmega161(L) 126 When writing serial data to the ATmega161, data is clocked on the rising edge of SCK. When reading data from the ATmega161, data is clocked on the falling edge of SCK. See Figure 80, Figure 81 and Table 49 for timing details. To program and verify the ATmega161 in the Serial Programming mode, the following sequence is recommended (see 4-byte instruction formats in Table 48): 1 ...
Page 127
... Table 47. Minimum Wait Delay after a Chip Erase Command Symbol t WD_ERASE Figure 80. Serial Programming Waveforms SERIAL DATA INPUT MSB PB5 (MOSI) SERIAL DATA OUTPUT MSB PB6 (MISO) SERIAL CLOCK INPUT PB7(SCK) SAMPLE ATmega161(L) value. WD_EEPROM Minimum Wait Delay 14 ms 3.4 ms Minimum Wait Delay 28 ms LSB LSB 127 ...
Page 128
... Boot Lock Bit1 4 = Boot Lock Bit2 5 = Boot Lock Bit11 6 = Boot Lock Bit12 7 = CKSEL0 Fuse 8 = CKSEL1 Fuse 9 = CKSEL2 Fuse B = SUT Fuse C = SPIEN Fuse D = BOOTRST Fuse ATmega161(L) 128 . (1) Instruction Format Byte 2 Byte 3 0101 0011 xxxx xxxx 100x xxxx xxxx xxxx xxxa aaaa ...
Page 129
... CLCL t Oscillator Period CLCL t SCK Pulse Width High SHSL t SCK Pulse Width Low SLSH t MOSI Setup to SCK High OVSH t MOSI Hold after SCK High SHOX t SCK Low to MISO Valid SLIV ATmega161( SLSH SHOX t SHSL = -40°C to 85° Min Typ ...
Page 130
... Respect to Ground .............................-1. Voltage on RESET with Respect to Ground ....-1.0V to +13.0V Maximum Operating Voltage ............................................ 6.6V DC Current per I/O Pin ............................................... 40 Current VCC and GND Pins ............................... 200.0 mA ATmega161(L) 130 *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and ...
Page 131
... Idle mode MHz WDT enabled WDT disabled - 2. 4.0V CC may exceed the related specification. Pins are not guaranteed to sink current greater OL ATmega161(L) Typ Max (1) V 0.3 CC (1) V 0 0 0 0.5 CC 0.6 0.5 8.0 980 500 120 3.0 1.2 9 15.0 <1 2.0 ...
Page 132
... If I exceeds the test condition greater than the listed test condition. 5. Minimum V for power-down is 2V. CC External Clock Drive Waveforms ATmega161(L) 132 may exceed the related specification. Pins are not guaranteed to source current OH Figure 82. External Clock VIH1 VIL1 (1) Table 50. External Clock Drive ...
Page 133
... CLCL 27.5 0.5t CLCL 27.5 0.5t CLCL 95 1.0t CLCL 105 1.0t CLCL 8 MHz Oscillator Min Max 185 230 2.0t 220 2.0t 230 2.0t ATmega161(L) Max Unit 8.0 MHz -30 ns (1) - (1) -40 ns -30 ns -30 ns (2) (2) -20 0.5t +20 ns CLCL (2) (2) -20 0 ...
Page 134
... ALE Low to RD Low LLRL 9 t Data Setup to RD High DVRH 10 t Read Low to Data Valid RLDV 11 t Data Hold After RD High RHDX ATmega161(L) 134 8 MHz Oscillator Min Max Min 310 355 3.0t CLCL 345 3.0t CLCL 35 3.0t CLCL 8 MHz Oscillator ...
Page 135
... CLCL 730 3.0t CLCL 4 MHz Oscillator Min Max Min 585 730 3.0t CLCL 375 1.5t 710 3.0t CLCL 730 3.0t CLCL ATmega161(L) Variable Oscillator Max Unit - CLCL -40 ns -20 ns Variable Oscillator Max Unit 0.0 4.0 MHz 2.0t -165 ...
Page 136
... ATmega161(L) 136 Figure 83. External Memory Timing (SRWn1 = 0, SRWn0 = 0) T1 System Clock Ø ALE Prev. addr. XX Address [15..8] Prev. data Data/Address [7.. Prev. data Data/Address [7.. Figure 84. External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 System Clock Ø 1 ALE Prev. addr. XX Address [15..8] Prev. data XX Address Data/Address [7 ...
Page 137
... Data/Address [7..0] Prev. data XX Address Note: 1. The ALE pulse in the last period (T4 - T7) is only present if the next instruction accesses the RAM (internal or external). The data and address will only change ALE is present (the next instruction accesses the RAM). ATmega161( Address Data 16 ...
Page 138
... Typical Characteristics ATmega161(L) 138 Analog Comparator offset voltage is measured as absolute offset. Figure 87. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 1.5 Figure 88. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. ...
Page 139
... Figure 90. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 1400 1200 1000 800 600 400 200 0 2 2.5 3 Sink and source capabilities of I/O ports are measured on one pin at a time. ATmega161( 25˚ 2.5 3 3.5 4 4.5 5 5 3.5 4 4.5 ...
Page 140
... ATmega161(L) 140 Figure 91. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 120 T = 25˚C A 100 T = 85˚ 0.5 1 1.5 Figure 92. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 25˚ 85˚ 0 2.5 3 3 4.5 5 2.5 3 1228D–AVR–02/07 ...
Page 141
... Figure 93. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 Figure 94. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 25˚ 85˚ 0.5 1 1.5 ATmega161( 25˚ 85˚ 1 ( 2.5 3 3.5 V ( 4.5 5 141 ...
Page 142
... ATmega161(L) 142 Figure 95. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 Figure 96. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 25˚ 85˚ 0 2. 25˚ 85˚ 1 2.7V CC 1.5 2 2.5 V (V) OH 1228D–AVR–02/07 ...
Page 143
... Figure 97. I/O Pin Input Threshold vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 1 0.5 0 2.7 Figure 98. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 ATmega161( 25˚ 25˚ 5.0 5.0 143 ...
Page 144
... UBRR0 $08 ($28) ACSR ACD $07 ($27) PORTE - $06 ($26) DDRE - $05 ($25) PINE - $04 ($24) Reserved $03 ($23) UDR1 $02 ($22) UCSR1A RXC1 $01 ($21) UCSR1B RXCIE1 $00 ($20) UBRR1 ATmega161(L) 144 Bit 6 Bit 5 Bit 4 Bit SP14 SP13 SP12 SP11 SP6 SP5 SP4 SP3 INT0 INT2 - - INTF0 INTF2 OCIE1A ...
Page 145
... Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. 1228D–AVR–02/07 ATmega161(L) 145 ...
Page 146
... BRPL k Branch if Plus BRGE k Branch if Greater or Equal, Signed BRLT k Branch if Less than Zero, Signed BRHS k Branch if Half-carry Flag Set BRHC k Branch if Half-carry Flag Cleared ATmega161(L) 146 Operation Flags Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← ...
Page 147
... BLD Rd, b Bit Load from T to Register SEC Set Carry CLC Clear Carry SEN Set Negative Flag CLN Clear Negative Flag 1228D–AVR–02/07 ATmega161(L) Operation Flags then PC ← None then PC ← None then PC ← None then PC ← None then PC ← None then PC ← ...
Page 148
... CLV Clear Two’s Complement Overflow SET Set T in SREG CLT Clear T in SREG SEH Set Half-carry Flag in SREG CLH Clear Half-carry Flag in SREG NOP No Operation SLEEP Sleep WDR Watchdog Reset ATmega161(L) 148 Operation Flags Z ← ← ← ← ← ← ← ...
Page 149
... Ordering Code Package ATmega161-4AC 44A ATmega161-4PC 40P6 ATmega161-4AI 44A ATmega161-4PI 40P6 ATmega161-8AC 44A ATmega161-8PC 40P6 ATmega161-8AI 44A ATmega161-8PI 40P6 Package Type ATmega161(L) Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) 149 ...
Page 150
... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATmega161(L) 150 B PIN 1 IDENTIFIER ...
Page 151
... San Jose, CA 95131 R 1228D–AVR–02/07 B PIN 1 IDENTIFIER TITLE 44A, 44-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATmega161(L) A COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE SYMBOL A – – 1.20 A1 0.05 – ...
Page 152
... Errata ATmega161 Rev. E ATmega161(L) 152 • PWM not Phase Correct • Increased Interrupt Latency • Interrupt Return Fails when Stack Pointer Addresses the External Memory • Writing UBBRH Affects both UART0 and UART1 • Store Program Memory Instruction May Fail 5. PWM not Phase Correct In phase correct PWM mode, a change from OCRx = TOP to anything less than TOP does not change the OCx output ...
Page 153
... Store Program Memory Instruction May Fail At certain frequencies and voltages, the store program memory (SPM) instruction may fail. Problem Fix/Workaround Avoid using the SPM instruction. ATmega161(L) 153 ...
Page 154
... Changes from Rev. 1228B-09/01 to Rev. 1228C-08/02 ATmega161(L) 154 This document contains a log on the changes made to the data sheet for ATmega161. 1 Package Drawing updated from rev rev Written “Not recommend in new designs” on features page. All page numbers refers to this document. ...
Page 155
... Timer/Counter Prescalers................................................................................... 38 8-bit Timer/Counters T/C0 and T/C2 .................................................................. 40 Timer/Counter1................................................................................................... 49 Watchdog Timer.................................................................................. 58 EEPROM Read/Write Access............................................................. 60 Prevent EEPROM Corruption ............................................................................. 62 Serial Peripheral Interface – SPI........................................................ 63 SS Pin Functionality............................................................................................ 65 Data Modes ........................................................................................................ 65 UARTs.................................................................................................. 69 Data Transmission.............................................................................................. 69 Data Reception ................................................................................................... 71 UART Control ..................................................................................................... 73 Baud Rate Generator.......................................................................................... 76 Double-speed Transmission ............................................................................... 78 Analog Comparator ............................................................................ 81 ATmega161(L) i ...
Page 156
... ATmega161(L) ii Internal Voltage Reference ................................................................ 83 Voltage Reference Enable Signals and Start-up Time ....................................... 83 Interface to External Memory ............................................................ 84 Using the External Memory Interface ................................................................. 88 I/O Ports............................................................................................... 89 Port A.................................................................................................................. 89 Port B.................................................................................................................. 91 Port B Schematics .............................................................................................. 94 Port C.................................................................................................................. 98 Port D................................................................................................................ 100 Port E................................................................................................................ 106 Memory Programming...................................................................... 110 Boot Loader Support......................................................................................... 110 Entering the Boot Loader Program ................................................................... 111 Capabilities of the Boot Loader ...
Page 157
... Errata ................................................................................................. 152 ATmega161 Rev. E .......................................................................................... 152 Data Sheet Change Log for ATmega161 ........................................ 154 Changes from Rev. 1228B-09/01 to Rev. 1228C-08/02 ................................... 154 Table of Contents .................................................................................. i ATmega161(L) iii ...
Page 158
... ATmega161(L) iv 1228D–AVR–02/07 ...
Page 159
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...