AT90S2313-4SI Atmel, AT90S2313-4SI Datasheet - Page 42

• Manufacturer Part Number: AT90S2313-4SI
• Description: MCU 2K FLASH 4MHZ 20-SOIC
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S2313-4SI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 1 x 8 bit
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Lead Free Status / Rohs Status: No

UART
Data Transmission
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AT90S2313
The AT90S2313 features a full duplex (separate Receive and Transmit Registers) Uni-
versal Asynchronous Receiver and Transmitter (UART). The main features are:
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A block schematic of the UART transmitter is shown in Figure 34.
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data
Register (UDR). Data is transferred from UDR to the Transmit Shift Register when:
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Figure 34. UART Transmitter
If the 10(11)-bit Transmitter Shift Register is empty, data is transferred from UDR to the
Shift Register. At this time the UDRE (UART Data Register Empty) bit in the UART Sta-
Baud Rate Generator that can Generate a Large Number of Baud Rates (bps)
High Baud Rates at Low XTAL Frequencies
8 or 9 Bits Data
Noise Filtering
Overrun Detection
Framing Error Detection
False Start Bit Detection
Three separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
A new character has been written to UDR after the stop bit from the previous
character has been shifted out. The Shift Register is loaded immediately.
A new character has been written to UDR before the stop bit from the previous
character has been shifted out. The Shift Register is loaded when the stop bit of the
character currently being transmitted has been shifted out.
0839I–AVR–06/02