SAK-TC1197-512F180E AC Infineon Technologies, SAK-TC1197-512F180E AC Datasheet - Page 39

• Manufacturer Part Number: SAK-TC1197-512F180E AC
• Description: IC MCU 32BIT 4MB FLASH BGA416-10
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAK-TC1197-512F180E AC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 219
• Program Memory Size: 4MB (4M x 8)
• Program Memory Type: FLASH
• Ram Size: 224K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 48x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 180.0 MHz
• Sram (incl. Cache): 224.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 48
• Program Memory: 4.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.5.2
The TC1197 includes two High-Speed Synchronous Serial Interfaces, SSC0 and SSC1.
Both SSC modules have the same functionality.
Figure 6
Figure 6
The SSC supports full-duplex and half-duplex serial synchronous communication up to
45 Mbit/s (@ 90 MHz module clock, Master Mode). The serial clock signal can be
generated by the SSC itself (Master Mode) or can be received from an external master
(Slave Mode). Data width, shift direction, clock polarity and phase are programmable.
This allows communication with SPI-compatible devices. Transmission and reception of
data are double-buffered. A shift clock generator provides the SSC with a separate serial
clock signal. One slave select input is available for slave mode operation. Eight
programmable slave select outputs (chip selects) are supported in Master Mode.
Data Sheet
DMA Requests
Address
Decoder
Interrupt
Control
Control
Clock
shows a global view of the Synchronous Serial interface (SSC).
High-Speed Synchronous Serial Interfaces
RIR
TIR
EIR
f
f
SSC
CLC
General Block Diagram of the SSC Interface
(Kernel)
Module
SSC
Master
Master
Master
Slave
Slave
Slave
Enable
M/S Select
SLSO[7:0]
SLSOANDO[7:0]
SLSOANDI[7:0]
SCLKA
SCLKB
SCLK
SLSI[7:1]
MRSTA
MRSTB
MTSR
MTSRA
MTSRB
MRST
35
Control
Port
MTSR
MRST
SCLK
SLSI[7:1]
SLSO[7:0]
SLSOANDO[7:0]
MCB06058_mod
Introduction
V1.1, 2009-05
TC1197