SAK-TC1197-512F180E AC Infineon Technologies, SAK-TC1197-512F180E AC Datasheet - Page 31

• Manufacturer Part Number: SAK-TC1197-512F180E AC
• Description: IC MCU 32BIT 4MB FLASH BGA416-10
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAK-TC1197-512F180E AC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 219
• Program Memory Size: 4MB (4M x 8)
• Program Memory Type: FLASH
• Ram Size: 224K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 48x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 180.0 MHz
• Sram (incl. Cache): 224.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 48
• Program Memory: 4.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

In TC1197 the PMU1 contains 2 Mbyte of Program Flash realized as one Flash bank. It
does not contain any Data Flash.
Since in TC1197 the two PMUs can work in parallel, further combinations of concurrent
operations are supported if those are operating on Flash modules in different PMUs, e.g.
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•
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Both, the Program Flash and the Data Flash, provide error correction of single-bit errors
within a 64-bit read double-word, resulting in an extremely low failure rate. Read
accesses to Program Flash are executed in 256-bit width, to Data Flash in 64-bit width
(both plus ECC). Single-cycle burst transfers of up to 4 double-words and sequential
prefetching with control of prefetch hit are supported for Program Flash.
The minimum programming width is the page, including 256 bytes in Program Flash and
128 bytes in Data Flash. Concurrent programming and erasing in Data Flash is
performed using an automatic erase suspend and resume function.
A basic block diagram of the Flash Module is shown in the following figure.
Figure 4
All Flash operations are controlled simply by transferring command sequences to the
Flash which are based on JEDEC standard. This user interface of the embedded Flash
is very comfortable, because all operations are controlled with high level commands,
such as “Erase Sector”. State transitions, such as termination of command execution, or
errors are reported to the user by maskable interrupts. Command sequences are
Data Sheet
Write Bus
Addr Bus
Control
Read Bus
Read data from Flash1 while accessing code from Flash0.
Read code or data from one Flash while the other Flash is busy with program or erase
operation.
Both Flash modules are concurrently busy with program or erase operation.
64
64
Basic Block Diagram of Flash Module
Flash Interface&Control Module
State Machine FCS
Flash Command
FIM
ECC Block
PMU
27
ECC Code
RD_DATA
Address
WR_DATA
Control
Flash FSI & Array
64
64
8
8
PF-Read
DF-Read
Microcode
256+32 bit
Buffers
FSRAM
256 byte
128 byte
Buffer
Buffer
64+8 bit
Page
Write
SFRs
FSI
and
and
Flash_BasicBlockDiagram _generic.vsd
Flash Array Module
Redundancy
Control
Bank 0
Bank 1
FAM
Flash
Data
Program
Flash
Voltage Control
Introduction
V1.1, 2009-05
Bank 0
Bank 1
TC1197