SAF-C515C-8EM CA Infineon Technologies, SAF-C515C-8EM CA Datasheet - Page 19

• Manufacturer Part Number: SAF-C515C-8EM CA
• Description: IC MCU 8BIT OTP MQFP-80-1
• Manufacturer: Infineon Technologies
• Series: C5xx/C8xxr

Specifications of SAF-C515C-8EM CA

• Core Processor: C500
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: OTP
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 4.25 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-SQFP
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: USART, SSC
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 3
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Packages: PG-MQFP-80
• Max Clock Frequency: 10.0 MHz
• Sram (incl. Cache): 2.25 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 8
• Program Memory: 64.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: F515C8EMCANP; F515C8EMCAXT; SAF-C515C-8EMCA; SAF-C515C-8EMCA; SAF-C515C-8EMCAIN; SAFC515C8EMCAX; SP000068749; SP000106399

CPU
The C515C is efficient both as a controller and as an arithmetic processor. It has
extensive facilities for binary and BCD arithmetic and excels in its bit-handling
capabilities. Efficient use of program memory results from an instruction set consisting
of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 6 MHz crystal,
58% of the instructions are executed in 1 s (10 MHz: 600 ns).
PSW
Special Function Register
Bit
CY
AC
F0
RS1
RS0
OV
F1
P
Data Sheet
D0
Bit No. MSB
H
D7
CY
H
Function
Carry Flag
Used by arithmetic instruction.
Auxiliary Carry Flag
Used by instructions which execute BCD operations.
General Purpose Flag
Register Bank select control bits
These bits are used to select one of the four register banks.
Overflow Flag
Used by arithmetic instruction.
General Purpose Flag
Parity Flag
Set/cleared by hardware after each instruction to indicate an
odd/even number of “one” bits in the accumulator, i.e. even parity.
RS1
0
0
1
1
D6
AC
H
RS0
0
1
0
1
D5
F0
H
RS1
D4
Function
Bank 0 selected, data address 00
Bank 1 selected, data address 08
Bank 2 selected, data address 10
Bank 3 selected, data address 18
(D0
H
15
H
RS0
)
D3
H
D2
OV
H
D1
F1
H
LSB
D0
Reset Value: 00
P
H
H
H
H
H
PSW
-07
-0F
-17
-1F
H
H
H
H
C515C
2003-02
H