UPD70F3745GJ-GAE-AX Renesas Electronics America, UPD70F3745GJ-GAE-AX Datasheet - Page 902

• Manufacturer Part Number: UPD70F3745GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3745GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 60K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
Standby
function
Reset
function
Clock
monitor
Low-
voltage
detector
(LVI)
Function
Releasing sub-
IDLE mode
Operating
status in sub-
IDLE mode
Emergency
operation mode
Reset function
RESF register
Hardware status
on RESET pin
input
CLM register
Internal
oscillator
LVIM register
LVIS register
To use for
internal reset
signal
To use for
interrupt
PEMU1 register This bit is not automatically cleared.
Details of
Function
When the sub-IDLE mode is released, 12 cycles of the subclock (about 366
elapse from when the interrupt request signal that releases the sub-IDLE mode is
generated to when the mode is released.
Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
To realize low power consumption, stop the A/D and D/A converters before
shifting to the sub-IDLE mode.
In emergency operation mode, do not access on-chip peripheral I/O registers
other than registers used for interrupts, port function, WDT2, or timer M, each of
which can operate with the internal oscillation clock. In addition, operation of
CSIB0 to CSIB5 and UARTA0 using the externally input clock is also prohibited in
this mode.
An LVI circuit internal reset does not reset the LVI circuit.
Only “0” can be written to each bit of this register. If writing “0” conflicts with
setting the flag (occurrence of reset), setting the flag takes precedence.
When the power is turned on, the following pin may output an undefined level
temporarily, even during reset.
• P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin
The OCDM register is initialized by the RESET pin input. Therefore, note with
caution that, if a high level is input to the P05/DRST pin after a reset release
before the OCDM.OCDM0 bit is cleared, the on-chip debug mode is entered. For
details, see CHAPTER 4 PORT FUNCTIONS.
Once the CLME bit has been set to 1, it cannot be cleared to 0 by any means
other than reset.
When a reset by the clock monitor occurs, the CLME bit is cleared to 0 and the
RESF.CLMRF bit is set to 1.
The internal oscillator can be stopped by setting the RCM.RSTOP bit to 1.
The clock monitor is stopped while the internal oscillator is stopped.
The internal oscillator cannot be stopped by software.
When the LVION and LVIMD bits to 1, the low-voltage detector cannot be stopped
until the reset request due to other than the low-voltage detection is generated.
When the LVION bit is set to 1, the comparator in the LVI circuit starts operating.
Wait 0.2 ms or longer by software before checking the voltage at the LVIF bit after
the LVION bit is set.
Be sure to clear bits 6 to 2 to “0”.
This register cannot be written until a reset request due to something other than
low-voltage detection is generated after the LVIM.LVION and LVIM.LVIMD bits
are set to 1.
Be sure to clear bits 7 to 1 to “0”.
If the LVIMD bit is set to 1, the contents of the LVIM and LVIS registers cannot be
changed until a reset request other than LVI is generated.
When the INTLVI signal is generated, confirm, using the LVIM/LVIF bit, whether
the INTLVI signal is generated due to a supply voltage drop or rise across the
detected voltage.
Cautions
APPENDIX E LIST OF CAUTIONS
μ
s)
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