UPD70F3745GJ-GAE-AX Renesas Electronics America, UPD70F3745GJ-GAE-AX Datasheet - Page 828

• Manufacturer Part Number: UPD70F3745GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3745GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 60K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
I
Notes 1. At the start condition, the first clock pulse is generated after the hold time.
Remark n = 0 to 2
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
2
SCL0n clock frequency
Bus free time
(Between start and stop conditions)
Hold time
SCL0n clock low-level width
SCL0n clock high-level width
Setup time for start/restart conditions
Data hold time
Data setup time
SDA0n and SCL0n signal rise time
SDA0n and SCL0n signal fall time
Stop condition setup time
Pulse width of spike suppressed by
input filter
Capacitance load of each bus line
C Bus Mode (T
2. The system requires a minimum of 300 ns hold time internally for the SDA0n signal (at V
3. If the system does not extend the SCL0n signal low hold time (t
4. The high-speed mode I
5. Cb: Total capacitance of one bus line (unit: pF)
Note 1
in order to occupy the undefined area at the falling edge of SCL0n.
needs to be satisfied.
mode I
• If the system does not extend the SCL0n signal's low state hold time:
• If the system extends the SCL0n signal's low state hold time:
Parameter
t
Transmit the following data bit to the SDA0n line prior to the SCL0n line release (t
250 = 1,250 ns: Normal mode I
SU
CBUS compatible
master
I
A
2
:
C mode
DAT
2
= −40 to +85°C, V
C bus so that it meets the following conditions.
≥ 250 ns
2
C bus can be used in the normal-mode I
DD
f
t
t
t
t
t
t
t
t
t
t
t
Cb
CLK
BUF
HD: STA
LOW
HIGH
SU: STA
HD: DAT
SU: DAT
R
F
SU: STO
SP
= EV
Symbol
DD
<99>
<100>
<101>
<102>
<103>
<104>
<105>
<106>
<107>
<108>
<109>
2
= AV
C bus specification).
REF0
= AV
MIN.
0
250
4.7
4.0
4.7
4.0
4.7
5.0
4.0
Note 2
0
−
−
−
−
Normal Mode
REF1
CHAPTER
, V
SS
= EV
MAX.
1000
100
300
400
−
−
−
−
−
−
−
−
−
−
SS
LOW
2
29
C bus system. In this case, set the high-speed
= AV
), only the maximum data hold time (t
20 + 0.1Cb
20 + 0.1Cb
SS
ELECTRICAL
100
= 0 V, C
MIN.
0
1.3
0.6
1.3
0.6
0.6
0.6
High-Speed Mode
Note 2
0
−
0
−
Note 4
Note 5
Note 5
L
= 50 pF)
0.9
MAX.
Rmax.
400
300
300
400
50
−
−
−
−
−
−
−
−
IHmin.
Note 3
SPECIFICATIONS
+ t
of SCL0n signal)
Page 812 of 892
SU:DAT
Unit
kHz
pF
μ
μ
μ
μ
μ
μ
μ
ns
ns
ns
μ
ns
= 1,000 +
s
s
s
s
s
s
s
s
HD
:
DAT
)