UPD70F3745GJ-GAE-AX Renesas Electronics America, UPD70F3745GJ-GAE-AX Datasheet - Page 901

• Manufacturer Part Number: UPD70F3745GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3745GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 60K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
Standby
function
Function
HALT mode
IDLE1 mode
Releasing
IDLE1 mode
IDLE2 mode
Releasing
IDLE2 mode
STOP mode
Releasing
STOP mode
Subclock
operation mode
Releasing
subclock
operation mode
Sub-IDLE mode
Releasing sub-
IDLE mode
Details of
Function
If the HALT instruction is executed while an unmasked interrupt request signal is
being held pending, the status shifts to HALT mode, but the HALT mode is then
released immediately by the pending interrupt request.
Insert five or more NOP instructions after the instruction that stores data in the
PSC register to set the IDLE1 mode.
If the IDLE1 mode is set while an unmasked interrupt request signal is being held
pending, the IDLE1 mode is released immediately by the pending interrupt
request.
An interrupt request signal that is disabled by setting the PSC.NMI1M,
PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and IDLE1 mode is not
released.
Insert five or more NOP instructions after the instruction that stores data in the
PSC register to set the IDLE2 mode.
If the IDLE2 mode is set while an unmasked interrupt request signal is being held
pending, the IDLE2 mode is released immediately by the pending interrupt
request.
The interrupt request signal that is disabled by setting the PSC.NMI1M,
PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and IDLE2 mode is not
released.
Insert five or more NOP instructions after the instruction that stores data in the
PSC register to set the STOP mode.
If the STOP mode is set while an unmasked interrupt request signal is being held
pending, the STOP mode is released immediately by the pending interrupt
request.
The interrupt request that is disabled by setting the PSC.NMI1M, PSC.NMI0M,
and PSC.INTM bits to 1 becomes invalid and STOP mode is not released.
When manipulating the CK3 bit, do not change the set values of the PCC.CK2 to
PCC.CK0 bits (using a bit manipulation instruction to manipulate the bit is
recommended). For details of the PCC register, see 6.3 (1) Processor clock
control register (PCC).
If the following conditions are not satisfied, change the CK2 to CK0 bits so that
the conditions are satisfied and set the subclock operation mode.
Internal system clock (f
When manipulating the CK3 bit, do not change the set values of the CK2 to CK0
bits (using a bit manipulation instruction to manipulate the bit is recommended).
For details of the PCC register, see 6.3 (1) Processor clock control register
(PCC).
Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
When the CPU is operating on the subclock and main clock oscillation is stopped,
accessing a register in which a wait occurs is disabled. If a wait is generated, it
can be released only by reset (see 3.4.8 (2)).
Following the store instruction to the PSC register for setting the sub-IDLE mode,
insert the five or more NOP instructions.
If the sub-IDLE mode is set while an unmasked interrupt request signal is being
held pending, the sub-IDLE mode is then released immediately by the pending
interrupt request.
The interrupt request signal that is disabled by setting the PSC.NMI1M,
PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and sub-IDLE mode is not
released.
CLK
) > Subclock (f
Cautions
XT
= 32.768 kHz) × 4
APPENDIX E LIST OF CAUTIONS
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