UPD70F3745GJ-GAE-AX Renesas Electronics America, UPD70F3745GJ-GAE-AX Datasheet - Page 577

• Manufacturer Part Number: UPD70F3745GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3745GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 60K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
Remarks 1. The STTn bit is 0 if it is read immediately after data setting.
Cautions concerning set timing
For master reception:
For master transmission: A start condition cannot be generated normally during the ACK period. Set to 1 during
For slave:
• Setting to 1 at the same time as the SPTn bit is prohibited.
• When the STTn bit is set to 1, setting the STTn bit to 1 again is disabled until the setting is cleared to 0.
Condition for clearing (STTn bit = 0)
• When the STTn bit is set to 1 in the communication
• Cleared by loss in arbitration
• Cleared after start condition is generated by master
• When the LRELn bit = 1 (communication save)
• When the IICEn bit = 0 (operation stop)
• After reset
reservation disabled status
device
STTn
0
1
2. n = 0 to 2
Start condition is not generated.
When bus is released (in STOP mode):
During communication with a third party:
In the wait state (when master device):
• This trigger functions as a start condition reserve flag. When set to 1, it releases the bus and then
If the communication reservation function is disabled (IICRSVn = 1)
• The IICFn.STCFn bit is set to 1 to clear the information set (1) to the STTn bit. This trigger does
A restart condition is generated after the wait state is released.
A start condition is generated (for starting as master). The SDA0n line is changed from high level to
low level while the SCL0n line is high level and then the start condition is generated. Next, after the
rated amount of time has elapsed, the SCL0n line is changed to low level.
If the communication reservation function is enabled (IICFn.IICRSVn bit = 0)
automatically generates a start condition.
not generate a start condition.
Cannot be set to 1 during transfer. Can be set to 1 only when the ACKEn bit has been
set to 0 and the slave has been notified of final reception.
the wait period that follows output of the ninth clock.
Even when the communication reservation function is disabled (IICRSVn bit = 1), the
communication reservation status is entered.
Start condition trigger
Condition for setting (STTn bit = 1)
• Set by instruction
CHAPTER 17 I
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C BUS
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