SAF-C165-L25F HA Infineon Technologies, SAF-C165-L25F HA Datasheet - Page 63

• Manufacturer Part Number: SAF-C165-L25F HA
• Description: IC MCU 16BIT ROM/LESS TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C165-L25F HA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: ASC, SSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Packages: PG-TQFP-100
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 2.0 KByte
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: F165L25FHAXT; SAF-C165-L25FHA; SAF-C165-L25FHAINTR; SAF-C165-L25FHATR; SAF-C165-L25FHATR; SAFC165L25FHAXT; SP000012870

Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
Parameter
Data valid to WR
Data hold after WR
ALE rising edge after
RD, WR
Address hold after WR
ALE falling edge to CS
CS low to Valid Data In
CS hold after RD, WR
ALE falling edge to
RdCS, WrCS (with RW-
delay)
ALE falling edge to
RdCS, WrCS (no RW-
delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
Data hold after RdCS
Data Sheet
3)
2)
3)
3)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
22
24
26
28
38
39
41
42
43
46
47
48
49
50
51
t
A
+
CC 24 +
CC 15 +
CC - 12 +
CC 0 +
CC - 8 -
CC 9 +
CC 19 +
CC - 6 +
CC 38 +
CC 63 +
CC 28 +
SR –
SR –
SR –
SR 0
t
C
+
t
min.
F
Max. CPU Clock
(100 ns at 20 MHz CPU clock without waitstates)
t
t
F
F
t
= 20 MHz
t
t
t
t
t
t
t
A
C
F
A
C
C
C
A
59
t
F
max.
–
–
–
–
10 -
47 +
t
–
–
–
20 +
45 +
–
–
–
–
C
+ 2
t
t
t
A
t
C
C
A
1 / 2TCL = 1 to 20 MHz
min.
2TCL - 26
+
TCL - 10
+
- 12 +
0 +
- 8 -
–
TCL - 16
+
TCL - 6
+
- 6
+
–
–
2TCL - 12
+
3TCL - 12
+
2TCL - 22
+
0
Variable CPU Clock
t
t
t
t
t
t
t
t
C
F
F
A
A
C
C
C
t
F
t
A
t
F
max.
–
–
–
–
10 -
3TCL - 28
+
–
–
–
2TCL - 30
+
3TCL - 30
+
–
–
–
–
t
t
t
C
C
C
t
+ 2
V2.0, 2000-12
A
t
A
C165
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns