SAF-C165-L25F HA Infineon Technologies, SAF-C165-L25F HA Datasheet - Page 49

• Manufacturer Part Number: SAF-C165-L25F HA
• Description: IC MCU 16BIT ROM/LESS TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C165-L25F HA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: ASC, SSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Packages: PG-TQFP-100
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 2.0 KByte
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: F165L25FHAXT; SAF-C165-L25FHA; SAF-C165-L25FHAINTR; SAF-C165-L25FHATR; SAF-C165-L25FHATR; SAFC165L25FHAXT; SP000012870

Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.
Table 12
Description
ALE Extension
Memory Cycle Time Waitstates
Memory Tristate Time
Note: Please respect the maximum operating frequency of the respective derivative.
AC Characteristics
Multiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
Parameter
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
Address float after RD,
WR (with RW-delay)
Address float after RD,
WR (no RW-delay)
RD, WR low time
(with RW-delay)
Data Sheet
Memory Cycle Variables
t
Symbol
t
t
t
t
t
t
t
t
A
5
6
7
8
9
10
11
12
+
t
CC 10 +
CC 4 +
CC 10 +
CC 10 +
CC - 10 +
CC –
CC –
CC 30 +
C
+
Symbol
t
t
t
A
C
F
t
F
min.
Max. CPU Clock
(120 ns at 25 MHz CPU clock without waitstates)
t
= 25 MHz
A
t
t
t
t
45
A
A
A
C
t
A
Values
TCL
2TCL
2TCL
max.
–
–
–
–
–
6
26
–
<ALECTL>
(15 - <MCTC>)
(1 - <MTTC>)
1 / 2TCL = 1 to 25 MHz
min.
TCL - 10
+
TCL - 16
+
TCL - 10
+
TCL - 10
+
- 10 +
–
–
2TCL - 10
+
Variable CPU Clock
t
t
t
t
t
A
A
A
A
C
t
A
max.
–
–
–
–
–
6
TCL + 6
–
V2.0, 2000-12
C165
Unit
ns
ns
ns
ns
ns
ns
ns
ns