SAF-C165-L25F HA Infineon Technologies, SAF-C165-L25F HA Datasheet - Page 62

• Manufacturer Part Number: SAF-C165-L25F HA
• Description: IC MCU 16BIT ROM/LESS TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C165-L25F HA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: ASC, SSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Packages: PG-TQFP-100
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 2.0 KByte
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: F165L25FHAXT; SAF-C165-L25FHA; SAF-C165-L25FHAINTR; SAF-C165-L25FHATR; SAF-C165-L25FHATR; SAFC165L25FHAXT; SP000012870

AC Characteristics
Demultiplexed Bus (Reduced Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
Parameter
ALE high time
Address setup to ALE
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
RD, WR low time
RD, WR low time
RD to valid data in
RD to valid data in
ALE low to valid data in
Address to valid data in
Data hold after RD
rising edge
Data float after RD rising
edge (with RW-delay
Data float after RD rising
edge (no RW-delay
Data Sheet
(with RW-delay)
(no RW-delay)
(with RW-delay)
(no RW-delay)
1)
1)
)
)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
5
6
8
9
12
13
14
15
16
17
18
20
21
t
A
+
CC 11 +
CC 5 +
CC 15 +
CC - 10 +
CC 34 +
CC 59 +
SR –
SR –
SR –
SR –
SR 0
SR –
SR –
t
C
+
t
min.
F
Max. CPU Clock
(100 ns at 20 MHz CPU clock without waitstates)
t
A
= 20 MHz
t
t
t
t
A
A
C
C
58
t
A
max.
–
–
–
–
–
–
22 +
47 +
45 +
t
57 +
2
–
36 +
2
15 +
2
A
t
t
t
A
A
A
+
+
+
+
t
t
t
C
t
t
t
C
C
C
F
F
1)
1)
1 / 2TCL = 1 to 20 MHz
min.
TCL - 14
+
TCL - 20
+
TCL - 10
+
- 10
+
2TCL - 16
+
3TCL - 16
+
–
–
–
–
0
–
–
Variable CPU Clock
t
t
t
t
t
t
A
A
A
A
C
C
max.
–
–
–
–
–
–
2TCL - 28
+
3TCL - 28
+
3TCL - 30
+
4TCL - 43
+ 2
–
2TCL - 14
+ 22
+
TCL - 10
+ 22
+
t
t
t
t
t
C
C
A
F
F
t
1)
1)
A
+
t
t
V2.0, 2000-12
A
A
+
t
C
t
C
C165
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns