SAK-XC164CM-16F20F BA Infineon Technologies, SAK-XC164CM-16F20F BA Datasheet - Page 62

• Manufacturer Part Number: SAK-XC164CM-16F20F BA
• Description: IC MCU 16BIT FLASH 64-LQFP
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAK-XC164CM-16F20F BA

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 64-LFQFP
• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 47
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 14x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: XC164x
• Core: C166S V2
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: ASC/CAN/SSC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 5
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK166, CA166, AR166, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Packages: PG-LQFP-64
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 8.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 14
• Program Memory: 128.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: B158-H8961-X-X-7600IN - KIT EASY XC164CMXC164CMUCANIN - KIT U-CAN STARTER XC164CM
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: SP000245661

The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal
same frequency as the master clock (
two:
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal
frequency as the CPU clock signal
Bypass Operation
When bypass operation is configured (PLLCTRL = 0x
the internal oscillator (input clock signal XTAL1) through the input- and output-
prescalers:
f
If both divider factors are selected as ‘1’ (PLLIDIV = PLLODIV = ‘0’) the frequency of
directly follows the frequency of
cycle of the input clock
The lowest master clock frequency is achieved by selecting the maximum values for both
divider factors:
f
Phase Locked Loop (PLL)
When PLL operation is configured (PLLCTRL = 11
enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (
the output divider (F = PLLMUL+1 / (PLLIDIV+1 × PLLODIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of
is locked to
of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because
f
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP (see formula and
Data Sheet
MC
MC
MC
, the timing must be calculated using the minimum TCP possible under the respective
=
=
f
CPU
f
f
OSC
OSC
f
=
MC
/ ((PLLIDIV + 1) × (PLLODIV + 1)).
/ ((3 + 1) × (14 + 1)) =
f
f
MC
OSC
=
f
/ 2. This factor is selected by bit CPSYS in register SYSCON1.
OSC
. The slight variation causes a jitter of
× F) which results from the input divider, the multiplication factor, and
f
OSC
.
f
OSC
f
OSC
f
CPU
so the high and low time of
Figure
/ 60.
f
CPU
.
60
=
16).
f
MC
) or can be the master clock divided by
B
) the on-chip phase locked loop is
B
f
f
MC
CPU
) the master clock is derived from
which also affects the duration
f
. The CPU clock can have the
MC
is constantly adjusted so it
f
f
MC
SYS
Electrical Parameters
is defined by the duty
which has the same
f
CPU
is derived from
Derivatives
V1.4, 2007-03
XC164CM
f
MC