SAK-XC164CM-16F20F BA Infineon Technologies, SAK-XC164CM-16F20F BA Datasheet - Page 61

• Manufacturer Part Number: SAK-XC164CM-16F20F BA
• Description: IC MCU 16BIT FLASH 64-LQFP
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAK-XC164CM-16F20F BA

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 64-LFQFP
• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 47
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 14x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: XC164x
• Core: C166S V2
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: ASC/CAN/SSC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 5
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK166, CA166, AR166, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Packages: PG-LQFP-64
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 8.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 14
• Program Memory: 128.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: B158-H8961-X-X-7600IN - KIT EASY XC164CMXC164CMUCANIN - KIT U-CAN STARTER XC164CM
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: SP000245661

4.4
These parameters describe the dynamic behavior of the XC164CM.
4.4.1
The internal operation of the XC164CM is controlled by the internal master clock
The master clock signal
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate
This influence must be regarded when calculating the timings for the XC164CM.
Figure 15
Note: The example for PLL operation shown in
Data Sheet
the example for prescaler operation refers to a divider factor of 2:1.
Phase Locked Loop Operation (1:N)
f
f
Direct Clock Drive (1:1)
f
f
Prescaler Operation (N:1)
f
f
OSC
MC
OSC
MC
OSC
MC
AC Parameters
Definition of Internal Timing
Generation Mechanisms for the Master Clock
f
MC
can be generated from the oscillator clock signal
59
Figure 15
refers to a PLL factor of 1:4,
TCM
Electrical Parameters
TCM
TCM
MCT05555
Derivatives
V1.4, 2007-03
XC164CM
f
OSC
f
MC
f
.
MC
via
.