SAK-XC164CM-16F20F BA Infineon Technologies, SAK-XC164CM-16F20F BA Datasheet - Page 20

• Manufacturer Part Number: SAK-XC164CM-16F20F BA
• Description: IC MCU 16BIT FLASH 64-LQFP
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAK-XC164CM-16F20F BA

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 64-LFQFP
• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 47
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 14x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: XC164x
• Core: C166S V2
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: ASC/CAN/SSC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 5
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK166, CA166, AR166, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Packages: PG-LQFP-64
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 8.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 14
• Program Memory: 128.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: B158-H8961-X-X-7600IN - KIT EASY XC164CMXC164CMUCANIN - KIT U-CAN STARTER XC164CM
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: SP000245661

3.2
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
Figure 4
Based on these hardware provisions, most of the XC164CM’s instructions can be
executed in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For
Data Sheet
CPU
M AC
P refetch
M ultiply
B ranch
FIFO
ID X 0
ID X 1
M A H
Q X 0
Q X 1
U nit
U nit
U nit
+ /-
+ /-
Central Processing Unit (CPU)
CPU Block Diagram
C S P
C P U C O N 1
C P U C O N 2
R eturn
M R W
M C W
M S W
M A L
S tack
Q R 0
Q R 1
+ /-
IP
IFU
D ivisio n U n it
M u ltip ly U n it
Z E R O S
D P P 0
D P P 1
D P P 2
D P P 3
P S W
M D C
M D H
Exception
Injection/
V E C S E G
Handler
B it-M a sk-G e n .
T FR
B a rre l-S h ifte r
18
S P S E G
S TK O V
S TK U N
O N E S
M D L
S P
+ /-
ADU
ALU
RF
DM U
PM U
G P R s
2-S tage
R 15
R 14
5-S tage
G P R s
R 1
R 0
B u ffer
R 15
R 14
P refetch
R 1
R 0
P ipeline
C P
G P R s
P ipeline
R 15
R 14
R 1
R 0
IPIP
W B
Functional Description
Peripherals
Flash/RO M
m ca04917_x.vsd
DPRAM
DSRAM
PSRAM
Derivatives
V1.4, 2007-03
EBC
G P R s
XC164CM
R 1 5
R 1 4
R 1
R 0