SAA-XC866L-1FRA AB Infineon Technologies, SAA-XC866L-1FRA AB Datasheet - Page 18

• Manufacturer Part Number: SAA-XC866L-1FRA AB
• Description: IC MCU 8BIT 4KB FLASH 38TSSOP
• Manufacturer: Infineon Technologies
• Series: XC8xxr

Specifications of SAA-XC866L-1FRA AB

• Core Processor: XC800
• Core Size: 8-Bit
• Speed: 86MHz
• Connectivity: LIN, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 38-TSSOP
• Data Bus Width: 8 bit
• Data Ram Size: 750 B
• Interface Type: UART, SSC
• Maximum Clock Frequency: 26.67 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3
3.1
The SAA-XC866 is based on a high-performance 8-bit Central Processing Unit (CPU)
that is compatible with the standard 8051 processor. While the standard 8051 processor
is designed around a 12-clock machine cycle, the SAA-XC866 CPU uses a 2-clock
machine cycle. This allows fast access to ROM or RAM memories without wait state.
Access to the Flash memory, however, requires an additional wait state (one machine
cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte
instructions.
The SAA-XC866 CPU provides a range of debugging features, including basic stop/start,
single-step execution, breakpoint support and read/write access to the data memory,
program memory and SFRs.
Figure 5
Data Sheet
Legacy External Interrupts (IEN0, IEN1)
Functional Description
Processor Architecture
Non-Maskable Interrupt
CPU Block Diagram
Program Memory
External Interrupts
External Data
Memory Wait
Memory
Reset
f
CCLK
Figure 5
16-bit Registers &
Memory Interface
Opcode Decoder
State Machine &
Power Saving
Core SFRs
Immediate
Opcode &
Controller
Registers
Interrupt
shows the CPU functional blocks.
15
Register Interface
Multiplier / Divider
Timer 0 / Timer 1
UART
ALU
Functional Description
SAA-XC866
External SFRs
Internal Data
V1.5, 2010-09
Memory