UPD78F0500MC-5A4-A Renesas Electronics America, UPD78F0500MC-5A4-A Datasheet - Page 623

• Manufacturer Part Number: UPD78F0500MC-5A4-A
• Description: MCU 8BIT FLASH SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500MC-5A4-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(1) Remainder data register 0 (SDR0)
Cautions 1. The value read from SDR0 during operation processing (while bit 7 (DMUE) of multiplier/divider
(2) Multiplication/division data register A0 (MDA0H, MDA0L)
Cautions 1. MDA0H is cleared to 0 when an operation is started in the multiplication mode (when
Address: FF62H, FF63H, FF64H, FF65H
Symbol
MDA0H
Symbol
MDA0L
SDR0 is a 16-bit register that stores a remainder. This register stores 0 in the multiplication mode and the
remainder of an operation result in the division mode.
SDR0 can be read by an 8-bit or 16-bit memory manipulation instruction.
Reset signal generation clears SDR0 to 0000H.
MDA0 is a 32-bit register that sets a 16-bit multiplier A in the multiplication mode and a 32-bit dividend in the
division mode, and stores the 32-bit result of the operation (higher 16 bits: MDA0H, lower 16 bits: MDA0L).
Address: FF60H, FF61H
Symbol
SDR0
2. SDR0 is reset when the operation is started (when DMUE is set to 1).
2. Do not change the value of MDA0 during operation processing (while bit 7 (DMUE) of
3. The value read from MDA0 during operation processing (while DMUE is 1) is not guaranteed.
MDA
MDA
031
015
Figure 19-3. Format of Multiplication/Division Data Register A0 (MDA0H, MDA0L)
control register 0 (DMUC0) is 1) is not guaranteed.
multiplier/divider control register 0 (DMUC0) is set to 81H).
multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the operation is executed,
but the result is undefined.
SDR
015
MDA
MDA
030
014
SDR
014
MDA
MDA
029
013
Figure 19-2. Format of Remainder Data Register 0 (SDR0)
FF65H (MDA0HH)
FF63H (MDA0LH)
SDR
013
MDA
MDA
028
012
After reset: 0000H
FF61H (SDR0H)
SDR
012
MDA
MDA
027
011
After reset: 0000H, 0000H
SDR
011
MDA
MDA
026
010
SDR
010
MDA
MDA
025
009
R
SDR
009
MDA
MDA
024
008
SDR
008
MDA
MDA
023
007
R/W
SDR
007
MDA
MDA
022
006
SDR
CHAPTER 19 MULTIPLIER/DIVIDER
006
MDA
MDA
021
005
FF64H (MDA0HL)
FF62H (MDA0LL)
SDR
005
MDA
MDA
020
004
FF60H (SDR0L)
SDR
004
MDA
MDA
019
003
SDR
003
MDA
MDA
018
002
SDR
002
MDA
MDA
017
001
SDR
001
MDA
MDA
016
000
SDR
000
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