UPD78F0500MC-5A4-A Renesas Electronics America, UPD78F0500MC-5A4-A Datasheet - Page 400

• Manufacturer Part Number: UPD78F0500MC-5A4-A
• Description: MCU 8BIT FLASH SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500MC-5A4-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
11.4.2 Setting overflow time of watchdog timer
counting again by writing “ACH” to WDTE during the window open period before the overflow time.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts
The following overflow time is set.
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is
Remarks 1. f
5. The watchdog timer continues its operation during self-programming and EEPROM emulation of
on the set value of bit 0 (LSROSC) of the option byte.
If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is released.
At this time, the counter is not cleared to 0 but starts counting from the value at which it was
stopped.
If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit 1 of the
internal oscillation mode register (RCM) = 1) when LSROSC = 0, the watchdog timer stops
operating. At this time, the counter is not cleared to 0.
the flash memory.
overflow time and window size taking this delay into consideration.
WDCS2
In HALT mode
In STOP mode
0
1
0
0
0
1
1
1
2. ( ): f
2. The watchdog timer continues its operation during self-programming and EEPROM
RL
prohibited.
emulation of the flash memory. During processing, the interrupt acknowledge time is
delayed. Set the overflow time and window size taking this delay into consideration.
: Internal low-speed oscillation clock frequency
Table 11-3. Setting of Overflow Time of Watchdog Timer
WDCS1
RL
= 264 kHz (MAX.)
0
0
1
1
0
0
1
1
Watchdog timer operation stops.
During processing, the interrupt acknowledge time is delayed.
Oscillator Can Be Stopped by Software)
LSROSC = 0 (Internal Low-Speed
WDCS0
0
1
0
1
0
1
0
1
2
2
2
2
2
2
2
2
10
11
12
13
14
15
16
17
/f
/f
/f
/f
/f
/f
/f
/f
RL
RL
RL
RL
RL
RL
RL
RL
(3.88 ms)
(7.76 ms)
(15.52 ms)
(31.03 ms)
(62.06 ms)
(124.12 ms)
(248.24 ms)
(496.48 ms)
Overflow Time of Watchdog Timer
Watchdog timer operation continues.
CHAPTER 11 WATCHDOG TIMER
LSROSC = 1 (Internal Low-Speed
Oscillator Cannot Be Stopped)
Set the
400