UPD78F0500MC-5A4-A Renesas Electronics America, UPD78F0500MC-5A4-A Datasheet - Page 102

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UPD78F0500MC-5A4-A

Manufacturer Part Number
UPD78F0500MC-5A4-A
Description
MCU 8BIT FLASH SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet

Specifications of UPD78F0500MC-5A4-A

Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0500MC-5A4-A
Manufacturer:
NEC
Quantity:
8 000
78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Data memory
space
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security IDs
Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see
Program
memory space
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security Settings).
Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory.
When boot swap is used:
Figure 3-5. Memory Map (
FEDFH
FFFFH
FEFFH
FEE0H
FAFFH
FB00H
7FFFH
FF00H
8000H
0000H
Special function registers
Internal high-speed RAM
General-purpose
32
Flash memory
32768
registers
1024
256
Reserved
(SFR)
8 bits
7 F F F H
7 C 0 0 H
7 B F F H
0 7 F F H
0 3 F F H
0 4 0 0 H
0 0 0 0 H
8 bits
8 bits
8 bits
to 0085H to 008EH.
Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the on-chip
debug security IDs to 0085H to 008EH and 1085H to 108EH.
μ
PD78F0503D, 78F0503DA, 78F0513D, and 78F0513DA)
Block 1FH
Block 01H
Block 00H
0FFFH
108FH
108EH
107FH
07FFH
008FH
008EH
007FH
003FH
1085H
1084H
1080H
1000H
0800H
0085H
0084H
0080H
0040H
0000H
7FFFH
1 KB
CHAPTER 3 CPU ARCHITECTURE
On-chip debug security
On-chip debug security
Option byte area
Option byte area
ID setting area
ID setting area
CALLF entry area
CALLT table area
Vector table area
Program area
Program area
Program area
2048
1905
10
10
64
64
5
5
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
Note 1
Note 1
Note 1
Note 1
Boot cluster 0
1FFFH
Boot cluster 1
Note 2
102

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