M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 551

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

External Buses
2-232
4.4 Connectable Memories
4.4.1 Operation Frequency and Access Time
Connectable memories depend upon the BCLK frequency f(BCLK). The frequency of f(BCLK) is equal to
that of the BCLK , and is contingent on the oscillator's frequency and on the settings in the system clock
select bits (bit 6 of address 0006
The following are the conditional equations for the connections. Meet these conditions minimally. Fig-
ures 4.4.1 and 4.4.2 show the relation between the frequency of BCLK and memory.
(1) Read cycle time (tCR)/write cycle time (tCW)
(2) Address access time [ta(A)]
(3) Chip select access time [ta(S)]
Read cycle time (tCR) and write cycle time (tCW) must satisfy the following conditional expressions:
• With the Wait option cleared
• With the Wait option selected
Address access time [ta(A)] must satisfy the following conditional expressions:
(a) Vcc = 5V
• With the Wait option cleared
• With the Wait option selected
(b) Vcc = 3V
• With the Wait option cleared
• With the Wait option selected
Chip select access time [ta(S)] must satisfy the following conditional expressions:
(a) Vcc = 5V
• With the Wait option cleared
• With the Wait option selected
tCR < 10
tCR < 2 X 10
ta(A) < 10
ta(A) < 2 X 10
ta(A) < 10
ta(A) < 2 X10
ta(S) < 10
ta(S) < 2 X10
* 65(ns)
* 140(ns) = td(BCLK-AD) + tsu(DB – RD) – th(BCLK – RD)
* 65(ns)
9
/f(BCLK) and tCW < 10
9
9
9
/f(BCLK) – 65(ns)*
/f(BCLK) – 140(ns)*
/f(BCLK) – 65(ns)*
= td(BCLK – AD) + tsu(DB – RD) – th(BCLK – RD)
= (address output delay time) + (data input setup time) – (RD signal output hold time)
= (address output delay time) + (data input setup time) – (RD signal output hold time)
= td(BCLK – CS) + tsu(DB – RD) – th(BCLK – RD)
= (chip select output delay time) + (data input setup time) – (RD signal output hold time)
9
9
9
/f(BCLK) and tCW < 2 X 10
9
/f(BCLK) – 140(ns)*
/f(BCLK) – 65(ns)*
/f(BCLK) – 65(ns)*
16
, and bits 6 and 7 of address 0007
9
/f(BCLK)
9
/f(BCLK)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16
).
M16C / 62A Group
Mitsubishi microcomputers