M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 473

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2-154
Watchdog Timer
2.11 Watchdog Timer Usage
2.11.1 Overview of the watchdog timer usage
The watchdog timer can detect a runaway program using its 15-bit timer prescaler. The following is an
overview of the watchdog timer usage.
(1) Watchdog timer start procedure
(2) Watchdog timer stop conditions
(3) Watchdog timer initialization
(4) Runaway detection
(5) Watchdog timer cycle
When reset, the watchdog timer is in stopped state. Writing to the watchdog timer start register
initializes the watchdog timer to 7FFF
timer, once started operating, cannot be stopped by any means other than stopping conditions.
The watchdog timer stops in any one of the following states:
(a) Period in which the CPU is in stopped state
(b) Period in which the CPU is in waiting state
(c) Period in which the microcomputer is in hold state
The watchdog timer is initialized to 7FFF
(a) When the watchdog timer writes to the watchdog timer start register while a count is in progress
(b) When the watchdog timer underflows
When the watchdog timer underflows, a watchdog timer interrupt occurs. In writing a program, write to
the watchdog timer start register before the watchdog timer underflows. The watchdog timer interrupt
occurs regardless of the status of the interrupt enable flag (I flag). In processing a watchdog timer
interrupt, set the software reset bit to “1” to reset software.
The watchdog timer cycle varies depending on the BCLK and the frequency division ratio of the
prescaler selected.
Table 2.11.1. The watchdog timer cycle
Note: An error due to the prescaler occurs.
CM07
0
0
0
0
0
1
Invalid
CM06
0
0
0
1
0
Invalid
Invalid
CM17
0
0
1
1
16
Invalid
Invalid
CM16
and causes it to start performing a down count. The watchdog
0
1
0
1
16
in the cases given below, and begins a down count.
16MHz
32kHz
8MHz
4MHz
1MHz
2MHz
BCLK
WDC7
Invalid
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
0
1
0
1
0
1
0
1
0
1
Approx. 262.1ms (Note)
Approx. 524.3ms (Note)
Approx. 131.1ms (Note)
Approx. 524.3ms (Note)
Approx. 262.1ms (Note)
Approx. 32.8ms (Note)
Approx. 65.5ms (Note)
Approx. 1.049s (Note)
Approx. 4.194s (Note)
Approx. 2.097s (Note)
Approx. 2s (Note)
M16C / 62A Group
Mitsubishi microcomputers
Period