PCIMX515DJM8C Freescale Semiconductor, PCIMX515DJM8C Datasheet - Page 82

• Manufacturer Part Number: PCIMX515DJM8C
• Description: MPU I.MX515 529-MABGAPGE
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of PCIMX515DJM8C

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 800MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-MABGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

1
2
3
4
Electrical Characteristics
4.7.7
This section describes the timing parameters of the I
module, and
82
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2CLK line is released.
C
IC10
IC12
IC11
I2CLK
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
b
ID
I2DAT
= total capacitance of one bus line in pF.
I2CLK cycle time
Hold time (repeated) START condition
Set-up time for STOP condition
Data hold time
HIGH Period of I2CLK Clock
LOW Period of the I2CLK Clock
Set-up time for a repeated START condition
Data set-up time
Bus free time between a STOP and START condition
Rise time of both I2DAT and I2CLK signals
Fall time of both I2DAT and I2CLK signals
Capacitive load for each bus line (C
I
2
IC2
Table 77
C Module Timing Parameters
START
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
lists the I
IC10
IC6
IC8
Parameter
IC1
2
IC10
C Module timing characteristics.
Table 77. I
IC5
IC4
b
Figure 48. I
)
2
C Module Timing Parameters
IC11
2
IC11
C Bus Timing
2
C Module.
IC7
1.65 V–1.95 V, 2.7 V–3.3 V
START
Min
250
4.0
4.0
4.0
4.7
4.7
4.7
Supply Voltage =
10
0
—
—
—
Figure 48
Standard Mode
1
3.45
depicts the timing of I
1000
Max
300
400
—
—
—
—
—
—
—
—
2
IC3
STOP
Freescale Semiconductor
20 + 0.1C
20 + 0.1C
Supply Voltage =
2.7 V–3.3 V
100
Fast Mode
Min
2.5
0.6
0.6
1.3
0.6
1.3
0.6
0
—
IC9
1
3
b
b
4
4
START
Max
0.9
300
300
400
—
—
—
—
—
—
—
—
2
C
2
Unit
pF
µ
µ
µ
µ
µ
µ
µ
ns
µ
ns
ns
s
s
s
s
s
s
s
s