DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 342

• Manufacturer Part Number: DF2377RVFQ33W
• Description: IC H8S MCU FLASH 3V 384K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2377RVFQ33W

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.12
This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration).
There are four bus masters⎯the CPU, DTC, DMAC, and EXDMAC * ⎯that perform read/write
operations when they have possession of the bus. Each bus master requests the bus by means of a
bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use
of the bus by means of a bus request acknowledge signal. The selected bus master then takes
possession of the bus and begins its operation.
Note: * The EXDMAC is not supported by the H8S/2375, H8S/2375R, H8S/2373, and
6.12.1
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a
bus request acknowledge signal to the bus master. If there are bus requests from more than one bus
master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus
master receives the bus request acknowledge signal, it takes possession of the bus until that signal
is canceled.
The order of priority of the bus mastership is as follows:
An internal bus access by internal bus masters except the EXDMAC * and external bus release, a
refresh when the CBRM bit is 0, and an external bus access by the EXDMAC * can be executed in
parallel.
If an external bus release request, a refresh request, and an external access by an internal bus
master occur simultaneously, the order of priority is as follows:
As a refresh when the CBRM bit in REFCR is cleared to 0 and an external access other than to
DRAM space by an internal bus master can be executed simultaneously, there is no relative order
of priority for these two operations.
Note: * The EXDMAC is not supported by the H8S/2375, H8S/2375R, H8S/2373, and
Rev.7.00 Mar. 18, 2009 page 274 of 1136
REJ09B0109-0700
(High) EXDMAC * > DMAC > DTC > CPU (Low)
(High) Refresh > EXDMAC * > External bus release (Low)
(High) External bus release > External access by internal bus master except EXDMAC * (Low)
Bus Arbitration
Operation
H8S/2373R.
H8S/2373R.