DF2377RVFQ33 Renesas Electronics America, DF2377RVFQ33 Datasheet - Page 766
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DF2377RVFQ33
Manufacturer Part Number
DF2377RVFQ33
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2377RVFQ33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit
1
0
15.3.6
SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and
selection of the transfer/receive clock source. For details on interrupt requests, refer to section
15.9, Interrupt Sources. Some bit functions of SCR differ in normal serial communication
interface mode and Smart Card interface mode.
Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit
7
6
Rev.7.00 Mar. 18, 2009 page 698 of 1136
REJ09B0109-0700
Bit Name
CKS1
CKS0
Bit Name
TIE
RIE
Serial Control Register (SCR)
Initial Value
0
0
Initial Value
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Clock Select 1 and 0:
These bits select the clock source for the on-chip
baud rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register setting
and the baud rate, see section 15.3.9, Bit Rate
Register (BRR). n is the decimal display of the
value of n in BRR (see section 15.3.9, Bit Rate
Register (BRR)).
Description
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled.
TXI interrupt request cancellation can be performed
by reading 1 from the TDRE flag, then clearing it to
0, or clearing the TIE bit to 0.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
RXI and ERI interrupt request cancellation can be
performed by reading 1 from the RDRF flag, or the
FER, PER, or ORER flag, then clearing the flag to
0, or by clearing the RIE bit to 0.
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