DF2377RVFQ33 Renesas Electronics America, DF2377RVFQ33 Datasheet - Page 765

• Manufacturer Part Number: DF2377RVFQ33
• Description: IC H8S MCU FLASH 3V 384K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2377RVFQ33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
7
6
5
4
3
2
Bit Name
GM
BLK
PE
O/E
BCP1
BCP0
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Section 15 Serial Communication Interface (SCI, IrDA)
Description
GSM Mode
When this bit is set to 1, the SCI operates in GSM
mode. In GSM mode, the timing of the TEND
setting is advanced by 11.0 etu (Elementary time
unit: the time for transfer of 1 bit), and clock output
control mode addition is performed. For details,
refer to section 15.7.8, Clock Output Control.
When this bit is set to 1, the SCI operates in block
transfer mode. For details on block transfer mode,
refer to section 15.7.3, Block Transfer Mode.
Parity Enable (enabled only in asynchronous
mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit
is checked in reception. In Smart Card interface
mode, this bit must be set to 1.
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
For details on setting this bit in Smart Card
interface mode, refer to section 15.7.2, Data
Format (Except for Block Transfer Mode).
Basic Clock Pulse 1 and 0
These bits select the number of basic clock periods
in a 1-bit transfer interval on the Smart Card
interface.
00: 32 clock (S = 32)
01: 64 clock (S = 64)
10: 372 clock (S = 372)
11: 256 clock (S = 256)
For details, refer to section 15.7.4, Receive Data
Sampling Timing and Reception Margin. S stands
for the value of S in BRR (see section 15.3.9, Bit
Rate Register (BRR)).
Rev.7.00 Mar. 18, 2009 page 697 of 1136
REJ09B0109-0700