DF2377RVFQ33 Renesas Electronics America, DF2377RVFQ33 Datasheet - Page 329
DF2377RVFQ33
Manufacturer Part Number
DF2377RVFQ33
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2377RVFQ33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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• Normal space access after DRAM space write access
Idle Cycle in Case of Normal Space Access after Continuous Synchronous DRAM Space
Access:
Note: In the H8S/2378 Group, the synchronous DRAM interface is not supported.
• Normal space access after a continuous synchronous DRAM space read access
While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM
space write access, idle cycle is inserted in the first read cycle. The number of states of the idle
cycle to be inserted is in accordance with the setting of the IDLC bit. It does not depend on the
DRMI bit in DRACCR. Figure 6.78 shows an example of idle cycle operation when the ICIS2
bit is set to 1.
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous
synchronous DRAM space read access is disabled. Idle cycle insertion after continuous
synchronous DRAM space read access can be enabled by setting the DRMI bit to 1. The
conditions and number of states of the idle cycle to be inserted are in accordance with the
settings of bits ICIS1, ICIS0, and IDLC in RCR. Figure 6.79 shows an example of idle cycle
operation when the DRMI bit is set to 1. When the DRMI bit is cleared to 0, an idle cycle is
UCAS, LCAS
Address bus
Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access
HWR, LWR
Data bus
RAS
RD
φ
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)
T
p
DRAM space read
T
r
T
c1
T
c2
Idle cycle
T
i
External space read
Rev.7.00 Mar. 18, 2009 page 261 of 1136
T
1
T
2
Section 6 Bus Controller (BSC)
T
3
DRAM space read
T
c1
REJ09B0109-0700
T
c2
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