HD64F2633RTE28 Renesas Electronics America, HD64F2633RTE28 Datasheet - Page 9

IC H8S MCU FLASH 256K 120-TQFP

HD64F2633RTE28

Manufacturer Part Number
HD64F2633RTE28
Description
IC H8S MCU FLASH 256K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of HD64F2633RTE28

Core Processor
H8S/2600
Core Size
16-Bit
Speed
28MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
73
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2633RTE28V
Manufacturer:
RENESAS
Quantity:
296
Part Number:
HD64F2633RTE28V
Manufacturer:
RENESAS
Quantity:
784
Item
2.6 Number of States
Required for Instruction
Execution
Table 2.5 Number of
Cycles in Instruction
Execution
2.7 Bus States During
Instruction Execution
Table 2.6 Instruction
Execution Cycles
3.3.5 Usage Notes
Page
283,
285,
286,
288
290
293 to
302
312,
313
Revisions (See Manual for Details)
Note 6 added
Notes: 6. The number of states may differ depending on the
product. For details, refer to the hardware manual of the
product in question.
:M deleted from legend
All instances of :M deleted from table
Newly added
Instruction
CLRMAC *
Instruction
LDMAC *
Instruction
MULXS
MULXU
Instruction
STMAC *
5
5
5
MULXU.B Rs,Rd
Mnemonic
CLRMAC
Mnemonic
LDMAC ERs,MACH
LDMAC ERs,MACL
Mnemonic
MULXS.B Rs,Rd
MULXS.W Rs,ERd H8S/2600
MULXU.W Rs,ERd H8S/2600
Mnemonic
STMAC MACH,ERd
STMAC MACL,ERd
H8S/2600
H8S/2000
H8S/2000
H8S/2600
H8S/2000
H8S/2000
Instruction
Fetch
I
1
Instruction
Fetch
I
1
1
Instruction
Fetch
I
2
2
2
2
1
1
1
1
Instruction
Fetch
I
1
1
Rev. 4.00 Feb 24, 2006 page vii of xiv
1
1
1
Branch
Address
Read
J
Branch
Address
Read
J
Branch
Address
Read
J
2
1
3
1
2
1
3
1
Branch
Address
Read
J
Stack
Operation
Stack
Operation
Stack
Operation
Stack
Operation
K
K
K
K
Byte Data
Access
L
Byte Data
Access
L
Byte Data
Access
L
Byte Data
Access
L
Word Data
Access
M
Word Data
Access
M
Word Data
Access
M
Word Data
Access
M
Internal
Operation
N
Internal
Operation
N
Internal
Operation
N
Internal
Operation
N
0 *
0 *
*
*
*
*
1
*
9
*
1
*
9
3
3
3
3
3
3
3
3
3
*
*
*
*
*
*
*
*
*
6
6
6
6
6
6
6
6
6

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