DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 744
DF2238RTF6
Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2238RTF6
Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6
HD64F2238RTF6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 16 I
9. Notes on I
10. Notes on IRIC Flag Clearance when Using Wait Function
Rev. 6.00 Mar. 18, 2010 Page 682 of 982
REJ09B0054-0600
If the rise time of the 9th SCL acknowledge exceeds the specification because the bus load
capacitance is large, or if there is a slave device of the type that drives SCL low to effect a
wait, issue the stop condition instruction after reading SCL and determining it to be low, as
shown below.
If the SCL rise time exceeds the designated duration or if the slave device is of the type that
keeps SCL low and applies a wait state when the wait function is used in the master mode of
the I
low, as shown below.
Clearing the IRIC flag to 0 when WAIT is set to 1 and SCL is being held at high level can
cause the SDA value to change before SCL goes low, resulting in a start condition or stop
condition being generated erroneously.
SDA
IRIC
SCL
2
C bus interface, read SCL and clear the IRIC flag after determining that SCL has gone
2
SCL
SDA
IRIC
C Bus Interface (IIC) (Option)
2
C Bus Interface Stop Condition Instruction Issuance
Figure 16.24 IRIC Flag Clearance in WAIT = 1 Status
VIH
9th clock
Figure 16.23 Timing of Stop Condition Issuance
As waveform rise is late,
[1] Determination of SCL = low
SCL is detected as low
V
SCL = low detected
High period secured
[1] Judgement that SCL = low [2] IRIC clearance
IH
SCL = high duration
maintained
[2] Stop condition instruction issuance
Stop condition
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